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PUT JOSH WEB-STREAM HERE. 4/30/2010 Iowa State University EE492 – Senior Design II. IRP Review: A TEST CHIP FOR ELECTROMIGRATION STUDIES Karl Peterson (EE), Emmanuel Owusu ( CprE ), and Joshua Ellis (EE). Our project is special…. International collaboration

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4 30 2010 iowa state university ee492 senior design ii


Iowa State University

EE492 – Senior Design II

IRP Review:A TEST CHIP FOR ELECTROMIGRATION STUDIESKarl Peterson (EE), Emmanuel Owusu (CprE), and Joshua Ellis (EE)

Our project is special
Our project is special…

  • International collaboration

  • Product conceptualization & specification in addition to design

  • Integrated circuit (IC) rather than system design

  • Research-orientated objectives

Problem statement
Problem Statement

  • Design a test chip to support ISU research on electromigration & IC reliability

  • The chip must include test structures composed of actual metal interconnects in a modern silicon process

  • Must be capable of interfacing with a controller to allow electrothermal conditions in the chip to be varied and monitored.

The big picture
The Big Picture

  • Electromigration – a complex physical phenomena that causes mechanical stress in metal interconnects

  • Important failure mechanism in ICs

  • Strong, non-linear dependence on current-density and temperature

  • Need models for electromigration that predict reliability under practical conditions

Electromigration in progress!

Electromigration testing
Electromigration testing

  • Subject interconnects to variable electrothermal stresses

  • Measure time-to-failure of many samples

  • Analyze statistics, develop models, fit data, etc.

  • Use accelerated lifetime technique

  • Very high temperatures and current densities!

Proposed solution
Proposed Solution

  • Proposed IC contains 8 identical metal test structures

  • Current-steering Digital-to-Analog Converter provides 0-25mA to test structure

  • On-die analog temperature sensing circuits

  • Open-circuit detection

  • Control logic with serial interface

  • Process technology:0.18 µm standard CMOS

Test structure
Test Structure

  • Single-layer metal interconnect with serpentine pattern

Test structure detail
Test structure – detail

Corners reinforced to mitigate current crowding

Current steering dac
Current-Steering DAC

  • Current range of 0 to 25 mA

  • 7 bit resolution

  • LSB Current – 200 µA

  • Current-Steering Architecture

    • Binary-weighted sources

    • Constant power

  • Open Circuit Detection

    • Two inverters on the output



Temperature sensor
Temperature sensor

  • Compact, CMOS-based sensor design

  • 5 sensor distributed throughout the floor plan

Control logic
Control Logic

  • Serial interface

  • Simple protocol

  • Low pin-count

Digital flow
Digital flow

  • Needed standard cell library for synthesis

  • Free, scalable library did not meet design rules of our process

  • Extensive work to customize , re-verify standard cells

Auxiliary blocks
Auxiliary blocks

  • Master current switch

  • Reference-distribution network

Physical design
Physical Design

  • Floorplan symmetry to prevent uncontrolled experimental variables

  • Significant redundancy and reinforcement of non-test blocks for reliability

  • Final design is 860 µm x 860 µm

Simulations verification
Simulations & Verification

  • Analog verification: relevant performance parameters for each block tested over full PVT range with 500-run statistical simulations

  • Digital verification: functional simulations, timing analysis

  • System-level, mixed-signal verification: several long transient simulations covering typical operation sequence

Top level functional simulation
Top-level Functional Simulation

#1 VDD rises

#2 Reference current starts

#3 <000> written to address reg.

#4 <0101010> written to address reg.

#5 master current switch enabled

#6 test current settles at predicted value

Backup slides test results
Backup slides – test results

  • DAC

  • Temperature sensor

  • Top-level functional