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Clocks and PLL. CS 3220 Fall 2014 Hadi Esmaeilzadeh hadi@cc.gatech.edu Georgia Institute of Technology Some slides adopted from Prof. Milos Prvulovic. Asynchronous vs. Synchronious. Glitches and delays are very hard to deal with People came up with synchronous circuits

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clocks and pll

Clocks and PLL

CS 3220

Fall 2014

Hadi Esmaeilzadeh

hadi@cc.gatech.edu

Georgia Institute of Technology

Some slides adopted from Prof. Milos Prvulovic

asynchronous vs synchronious
Asynchronous vs. Synchronious
  • Glitches and delays are very hard to deal with
  • People came up with synchronous circuits
    • There is a clock, all FFs trigger on clock edge
    • All signals only matter at the clock edge
    • Glitches and delays don’t matter, as long asnew value stabilizes before the next clock edge
    • The clock signal had better not have any glitches!
  • Alternative: asynchronous circuits – no clock
    • Either design a glitch-free circuit, or
    • Generates a glitch-free “ready” signal when outputs are ready, use that to trigger next FF
    • Not easy to get the timing of the “ready” signal right

Lecture 4: Clocks and PLLs

clocking
Clocking
  • We will make synchronous (clocked) designs
    • All FFs triggered by the same clock signal
    • No need to worry about glitches
  • What should be the clock frequency?
    • Clock Cycle Time must be long enough toaccommodate delays along all paths in our design
    • Quartus compiler automatically computes these delays
    • So if our clock is too fast we get a Critical Warning
  • Do not overclock designs you submit for Projects!
    • Will lose points for doing that!
    • Design may not work at a different temperature, another instance of the DE-1 board, etc.

Lecture 4: Clocks and PLLs

timing requirements
Timing Requirements
  • Clock cycle time computed from clock frequency
  • Delays on all paths computed from your design
  • Slack – time left over after all delays
  • Timing requirement => no negative slack
  • Project designs must meet timing requirements
    • Will lose points for submitting an overclocked design
    • Design may work when you test it!
    • But if it does not meet timing requirements,it is not guaranteed to work at different temperaturesor on other boards

Lecture 4: Clocks and PLLs

what to use as a clock signal
What to use as a clock signal
  • The board has a 50MHz clock (CLOCK_50)
    • There are two others, at 24MHz and a 27MHz
  • Will likely need a different clock frequency?
  • Clock divider can get us some lower frequencies
    • E.g. what if we flip a FF every cycle at 50MHz?
    • We get a 25MHz clock signal!
  • But what if we want 40MHz or 85MHz?
  • Answer: PLL (Phase-Locked Loop)

Lecture 4: Clocks and PLLs

what is a pll
What is a PLL?
  • Phase-Locked Loop
    • Input: a clock signal at some frequency (e.g. 50MHz)
    • PLL can multiply frequency then divide it (50MHz*X/Y)
      • Cheap PLL: X and Y are fixed, can get some particular frequency
      • Fancy PLL: X and Y can be programmed
    • Lucky us – our board has a really fancy PLL 
      • Using the 50MHz clock as input, we can get a frequencythat is just a bit lower to what we want
      • Why not just a bit higher than what we want?
    • Can also control the duty cycle and phase shift
      • Duty cycle: What part of the cycle is clock HIGH (default is 50%)
      • Phase shift: Clock edge can be delayed relative to another clock
      • Don’t mess with these settings
      • If you need to change them, probably you are doing something wrong

Lecture 4: Clocks and PLLs

using plls
Using PLLs
  • PLLs is a specialized circuit, can’t synthesizea really good one using logic gates and FFs
  • But our FPGA chip includes 4 such circuits
    • We just need to get Quartus to use one!
    • Use a Verilog module that maps to a PLL,then connect it properly
  • Use QuartusMegaWizard to generate PLL code
    • Tools -> Mega Wizard Plug-In Manager
    • Select “Create a new custom megafunction variation”
    • In the dialog, select Verilog, a file name (e.g. PLL.v) and select Installed Plug-Ins -> I/O -> ALTPLL

Lecture 4: Clocks and PLLs

configuring altpll
Configuring ALTPLL
  • Now we get to configure the PLL
    • Leave speed grade alone (our chip is speed grade 7)
    • Set input frequency to 50MHz (we will use CLOCK_50)
    • Leave PLL type and operation mode alone
    • On the next page, disable “areset” signal option,leave the option for the “locked” signal enabled,and enter 5000 in the “Hold locked input low…” box
    • Don’t create any additional clock inputs
    • For output clocks, we will only use c0
    • Enter output clock frequency
      • You give it a frequency, “Actual settings” displays what it can do
      • Leave phase shift at 0 degrees and duty cycle at 50% for now
    • Later on, enable creation of the “Instantiation Template File” and click “Finish”

Lecture 4: Clocks and PLLs

adding a pll to our circuit
Adding a PLL to our circuit
  • Need to create a PLL instance and wire it up
    • Right-click in your Verilog code
    • Select “Insert Template”
    • In the dialog, go to “Megafunctions -> Instances”,find the PLL and select it, then click “Insert”
    • Now change the paramaters to match our processor
      • E.g. we want “.inclk0(CLOCK_50)”
      • Connect .c0 clock output to what you use as a clock (e.g. “.c0(clk)”)
  • Now we have a clock signal for the FFs in our design
    • Remember – synchronous design
    • All FFs clocked with the same clock!
    • Don’t use CLOCK_50 for some FFs and the PLL output for others!
  • Hmmm… what is this “locked” signal that PLL is producing?

Lecture 4: Clocks and PLLs

the locked pll signal
The “locked” PLL signal
  • PLL takes time to achieve requested frequency
    • While it is “locking in”, clock frequency is unstable
      • Some clock cycles too long (which is OK)
      • But some are too short (not good, remember timing requirements)
    • Our design should wait until the clock is safe to use!

always @(posedgeclk)

if(locked)

state <= …;

Lecture 4: Clocks and PLLs

putting it all together
Putting it all together

wire clk,locked;

PllmyPll(.inclk0(CLOCK_50),.c0(clk),

.locked(locked));

wire reset=(!locked)|!KEY[0];

always @(posedgeclk or posedge reset)

if(reset) begin

some_var<=some_var_init_val;

end else begin

your normal code, e.g.some_var <=…;

end

Lecture 4: Clocks and PLLs

resulting design
Resulting design:

Lecture 4: Clocks and PLLs

do this for all reg variables
Do this for allreg variables?
  • No, just the ones that matter
    • Some FFs need no initialization
      • Can leave those uninitialized and/or assign w/o checking PLL lock
  • But easier to just init and lock-check everything
    • If something needed initialization and/or lock-check but youdidn’t do it, the resulting bug is very hard to find
    • Heisenbug – sometimes it manifests, sometimes not
    • Whether a Heisenbug-infested design works or not depends on:
      • Value that FF starts with
      • How many cycles the PLL needs to lock
      • Manufacturing variations (exact timing of gates on your board)
      • Temperature (changes speed of gates)
      • And many other things

Lecture 4: Clocks and PLLs

what if i do this
What if I do this…

always @(posedgeclkor negedge lock)

if(!lock) begin

some_var<=some_var_init_val;

end else begin

your normal code, e.g.some_var <=…;

end

  • Same behavior… but…
    • This puts initialization logic on every path!
    • With “or negedge lock”, uses SET/CLR inputs on FFs

Lecture 4: Clocks and PLLs

note the difference
Note the difference!

Lecture 4: Clocks and PLLs

our on off switch again
Our On/Off Switch Again

module Lectures(LEDG, KEY);

output [0:0] LEDG;

input [3:0] KEY;

wire flip = ! KEY[3];

reg state;

always @(posedge flip)

state <= !state;

assign LEDG[0]=state;

endmodule

  • Is LEDG[0] initially on or off?

Lecture 4: Clocks and PLLs

initialization
Initialization

module Lectures(LEDG, KEY);

output [0:0] LEDG;

input [3:0] KEY;

wire flip = ! KEY[3];

reg state=0;

always @(posedge flip)

state <= !state;

assign LEDG[0]=state;

endmodule

The initial value of the “state”flip-flop should be zero

Lecture 4: Clocks and PLLs

initialization1
Initialization

module Lectures(LEDG, KEY);

output [0:0] LEDG;

input [3:0] KEY;

wire flip = ! KEY[3];

reg state;

initial begin

state=0;

end

always @(posedge flip)

state <= !state;

assign LEDG[0]=state;

endmodule

Same as previous slide, but allows formore complex initialization

Usually you put the “initial” statement

where the “always” block for that FF is

Lecture 4: Clocks and PLLs

initialization and reset
Initialization and Reset

module Lectures(LEDG, KEY);

output [0:0] LEDG;

input [3:0] KEY;

wire flip = ! KEY[3];

wire reset=!KEY[2];

reg state;

initial begin

state=0;

end

always @(posedge flip or posedge reset)

if(reset)

state<=0;

else

state <= !state;

assign LEDG[0]=state;

endmodule

Initialize the state whenthe board is turned on or programmed!

Allows us to initialize the stateusing a reset signal!

Lecture 4: Clocks and PLLs

glitches
Glitches
  • Signals can briefly have wrong values
    • Due to logic delays and how they play together
  • Example: 4-bit adder
    • Inputs were 0000 and 0000, output is 0000
    • Inputs change to 0001 and 1111, output stays 0000
    • Actually, output changes briefly, then becomes 0000
  • Why?
    • Let’s just look at the MSB part of the adder
    • Takes two inputs and carry, produces output bit
    • Problem: takes time for carry to arrive,meanwhile MSB output is 1

Lecture 4: Clocks and PLLs

glitch demo
Glitch demo

reg [3:0] cntr1,cntr2;

initial begin

cntr1 = 4'h0;

cntr2 = 4'h0;

end

always @(posedgemykey[3]) begin

cntr1 <= cntr1+4'h1;

cntr2 <= cntr2-4'h1;

end

wire [3:0] sum = cntr1 + cntr2; // Should always be 0000

wire sumnz = (sum != 0); // Should always be 0

reg [9:0] nzCnt;

initial nzCnt = 0;

always @(posedgesumnz) nzCnt <= nzCnt + 9'd1;

assign LEDG = {sumnz,3'b0,sum};

assign LEDR=nzCnt;

Two counters that start at 0 and

count in opposite directions

Counts how many times sumnz became 1

Lecture 4: Clocks and PLLs