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MIPS processor continued

MIPS processor continued. In Class Exercise – Supporting Jump Register. Supporting jr Instruction. Performance. Assume that Memory access: 200ps ALU and adders: 100 ps Register file read: 50ps Register file write: 50ps (the clk-to-q delay) PC update: 10ps (the clk-to-q delay)

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MIPS processor continued

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  1. MIPS processor continued

  2. In Class Exercise – Supporting Jump Register week-14-1.ppt

  3. Supporting jr Instruction

  4. Performance • Assume that • Memory access: 200ps • ALU and adders: 100 ps • Register file read: 50ps • Register file write: 50ps (the clk-to-q delay) • PC update: 10ps (the clk-to-q delay) • The setup time of DFFs: 10ps • Other parts do not have delay • How fast is • An R-type instruction? • A lw instruction? • A sw instruction? • A beq instruction? • Need to find the critical path – the longest path

  5. R-type • So, the clock needs to be at least 10+200+50+100+10 = 370ps • Will there be a problem if the next instruction is also an R-type instruction, considering that the register is written and stable only after the next rising edge of the clock? • Figure not to the exact scale instruction ready register ready ALU ready register written PC ready

  6. lw • So, the clock needs to be at least 10+200+50+100+200+10 = 570ps • Figure not to the exact scale instruction ready Data mem ready register ready ALU ready register written PC ready

  7. beq • So, it is 10+200+50+100+10 = 370ps • Figure not to the exact scale instruction ready register ready ALU ready PC ready Adder 1 ready Adder 2 ready

  8. Clock cycle • So, how long should the clock cycle be? • Is it efficient?

  9. Control Signals • Control signals include ALUCtrl and the signals to control the 2-1 selectors • They are generated according to the current instruction, using the opcode [31-27] and the funct [5-0] field in the instruction.

  10. Datapath for Memory, R-type and Branch Instructions, plus the control signals

  11. The Effect of Control Signals

  12. Table for Control Line Setting Note: Branch is anded with ALU zero output to produce PCSrc

  13. Table for Control Line Setting

  14. Truth Table for Control Function

  15. Implementation Using PLA R lw sw beq The way to read this -- There are only 4 possible combination of inputs

  16. MIPS ALU unit

  17. ALU Control • Use Opcode to get ALUOp, then combine ALUOp with Funct • Two levels of decoding, more efficient • Assume ALUOp has been determined as such for each instruction week-13-3.ppt

  18. One Implementation ALU control bit 3 is always 0 for this set of instructions

  19. Supporting Jump Instruction

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