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This document outlines a VHDL implementation of the Greatest Common Divisor (GCD) algorithm for calculating the GCD of two integers. The design follows a behavioral architecture where a FSM (Finite State Machine) and a stack are used to control the process. The algorithm is implemented using recursive principles, allowing it to handle unsigned integers effectively. An example is included to demonstrate the usage of the GCD function with sample inputs, illustrating its capability and practical application in digital system design.
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Aplicações práticas Divisor máximo de dois inteiros
Begin x x 1 2 y3 y1,y2,z y1,y4,z End Divisor máximo de dois inteiros unsigned int gcd(unsigned int A, unsigned int B) { if (B > A) return gcd(B,A); else if (B==0) return A; else return gcd(B,A%B); } Z a0=0 1 if (B>A) 0 if (B==0) 0 a3=3 a1=1 a2=2 1 a4=4 y1 Data_A=B; y2 Data_B=A; y3 result=A; y4 Data_B = A%B;
unsigned int gcd(unsigned int A, unsigned int B) { if (B > A) return gcd(B,A); else if (B<=0) return A; else return gcd(B,A%B); } Exemplo cout << “The greatest common divisor is "; cout << gcd(120,164) << endl; The greatest common divisor is 4
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity greatest_common_div is generic (stack_size : integer ); Port ( clk25 : in std_logic; rst : in std_logic; A_in : in std_logic_vector(7 downto 0); B_in : in std_logic_vector(7 downto 0); result : out std_logic_vector(7 downto 0)); end greatest_common_div; architecture Behavioral of greatest_common_div is type MODULE_TYPE is (z0,z1); signal NM: MODULE_TYPE; type STATE_TYPE is (a0, a1, a2, a3, a4, a5); signal N_S: STATE_TYPE; Begin x x 1 2 y3 y1,y2,z y1,y4,z End Z a0=0 1 if (B>A) 0 if (B==0) 0 a3=3 a1=1 a2=2 1 a4=4 y1 Data_A=B; y2 Data_B=A; y3 result=A; y4 Data_B = A%B;
---------------------------------- for stack begin type stack is array(0 to stack_size) of STATE_TYPE; signal FSM_stack : stack; signal stack_counter : integer range 0 to stack_size; signal inc : std_logic; signal dec : std_logic; ---------------------------------- for stack end ---------------------------------- for stack of modules begin type Mstack is array(0 to stack_size) of MODULE_TYPE; signal M_stack : Mstack; ---------------------------------- for stack of modules end signal A,B,R,Data_A,Data_B: std_logic_vector(7 downto 0); begin
---------------------------------- for stack begin process(clk25,rst) begin if rst = '1' then stack_counter <= 0; FSM_stack(stack_counter) <= a0; M_stack(stack_counter) <= z0; elsif rising_edge(clk25) then if inc = '1' then if stack_counter = stack_size then else stack_counter <= stack_counter + 1; FSM_stack(stack_counter+1) <= a0; FSM_stack(stack_counter) <= N_S; M_stack(stack_counter+1) <= NM; end if; elsif dec = '1' then stack_counter <= stack_counter - 1; else FSM_stack(stack_counter) <= N_S; end if; end if; end process; ---------------------------------- for stack end
process (rst, clk25) begin if rst = '1' then Data_A <= A_in; Data_B <= B_in; result <= (others => '0'); elsif falling_edge(clk25) then case M_stack(stack_counter) is when z0 => case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; A <= Data_A; B <= Data_B; if Data_B > Data_A then N_S <= a1; elsif Data_B = "00000000" then N_S <= a2; else N_S <= a3; end if; when a1 => dec <= '0'; NM <= z0; inc <= '1'; Data_A <= B; Data_B <= A; N_S <= a5; when a2 => dec <= '0'; inc <= '0'; N_S <= a5; result <= A; when a3 => dec <= '0'; inc <= '1'; NM <= z1; N_S <= a4; when a4 => dec <= '0'; inc <= '1'; NM <= z0; Data_B <= R; Data_A <= B; N_S <= a5; when a5 => dec <= '0'; N_S <= a5; inc <= '0'; if stack_counter > 0 then dec <= '1'; else dec <= '0'; end if; when others => null; end case; Begin x x 1 2 y3 y1,y2,z y1,y4,z End Z a0=0 1 if (B>A) 0 if (B==0) 0 a3=3 a1=1 a2=2 1 a4=4 y1 Data_A=B; y2 Data_B=A; y3 result=A; y4 Data_B = A%B;
when z1 => case FSM_stack(stack_counter) is when a0 => dec <= '0'; inc <= '0'; if A >= B then N_S <= a1; else N_S <= a2; end if; when a1 => dec <= '0'; inc <= '0'; A <= A - B; N_S <= a0; when a2 => dec <= '0'; inc <= '0'; N_S <= a3; R <= A; when a3 => dec <= '0'; inc <= '0'; N_S <= a3; if stack_counter > 0 then dec <= '1'; else dec <= '0'; end if; when others => null; end case; when others => null; end case; end if; end process; end Behavioral;
