Verilog1_merged

1. Verilog

2. Overview • LogicDesignreview • BasicBuildingBlocks • DesignExamples:Incrementer,Fifo • Verilog:CodingBasicblocks • Useof Modules • Gates,Mux/Demux,Registers • DataValues • CounterExample

3. LogicDesignReview RegisterTransferLevel (RTL)Design

4. LogicDesign • BasicbuildingblocksforLogic designare • Gates • Muxes/Demuxes • Registers/Memory • ArithmeticOperations(Adder, Subtracter,Multipliersetc.) • Statemachines • AnycombinationsofAbove

5. Gates Inputs Outputs

6. Input[N:0] Clock Reset Output[N:0] Clock Input[N:0] 3 4 5 6 Output[N:0] x 3 4 5

7. Input[N:0] Clock Enable Output[N:0] Clock Input[N:0] 3 4 5 6 Output[N:0] x 5 Enable

8. SelectLines/Address Output Inputs

9. Address[N:0] DataOut[K:0] Write DataIn[K:0] RegistersFile

10. Address[N:0] DataOut[K:0] Write DataIn[K:0] MEMORY RegistersFile

11. Input1[N:0] Input2[N:0] Output[N+1:0] Adder/ Subtracter Cin Add/Sub Saturate Input1[N:0] Input2[N:0] Output[2N:0] Multiplier Signed/Unsigned Saturate

12. MakingnewModules,Using ExistingModules • DesignExamples • Example1: • Asimpledecrementercapable of countingnumberofclockcycles downtozero. • Example2: • AfourdeepFIFO

13. Decrementer Initial Value[N:0] Decrement -- Count Load Enable Clock Reset

14. FourdeepFIFO Datain[N:0] Push Dataout[N:0 FIFOFull ==4 Increment Pop counter Decrement FIFOEmpty ==0

15. ++ -- Increment Decrement Count Increment counter Decrement

16. FIFO Datain[N:0] Push Dataout[N:0 FIFOFull ==4 Increment Pop counter Decrement FIFOEmpty ==0

17. FIFO DMA PROCESSORA MEMORY SDRAM PROCESSORB MEMORY

18. Othercomponents Somewayto configure FilterTaps Somewayto takeOutput Somewayto provideInput FIRFilter Somewayto takeOutput Somewayto provideInput FFT Somewayto takeOutput Somewayto provideInput Error Correction

19. Verilog

20. Verilog IntroductiontoModules

21. Verilog Module:Areasonablesize replicate-ableblocke.g.FIFO, counteranddecrementerthatwe coveredaregoodcandidates.

22. FIFO DMA PROCESSORA MEMORY SDRAM PROCESSORB MEMORY

23. fifo.v data_in push data_out fifo_full pop fifo_empty

24. fifo.v counter.v

25. modulecounter( inputinput output[3:0] increment, decrement, count ); Codeformode endmodule modulefifo( input input input data_in, push, pop, [15:0] lingCounter output[15:0] data_out, output output ); fifo_full, fifo_empty ThecodeformodelingFIFOhere endmodule

26. modulecounter( inputinput output[3:0] increment, decrement, count ); Codeformode endmodule wirepush; wirepop; wire[3:0]count; lingCounter countercounter_inst1( .increment(push), .decrement .count ); (pop), (count) counter

27. Summary • Ablocklevelhierarchycanbe modeledasmodules. • Moduleisthebasicbuilding block. • Amodulecanbeinstantiated insideanothermodule. • Modulecanbereplicatedwitha differentinstancename.

28. Verilog

29. Verilog Basicbuildingblocks

30. BasicBuildingBlocks • BasicbuildingblocksforLogic designare • Gates • Muxes/Demuxes • Registers/Memory • ArithmeticOperations(Adder, Subtracter,Multipliersetc.) • Statemachines

31. Whatwearetryingtodo? Wearetryingtomodelour buildingblocksusingwordsand charactersorganizedinaset offiles

32. ModelingGates

33. ModelingMuxes/Demuxes always@(*) begin addr case(addr) endcase end MUX

34. DataValues 8’hXA 8’bXXXX_1010 8’hA 8’d10 8’b0000_1010 Underscores areignored BaseFormat (b,o,d,h) Width X’sshowdon’t carevalues

35. ModelingMuxes/Demuxes always@(*) begin addr case(addr) endcase end DEMUX

36. ModelingMuxes/Demuxes addr always@(*) begin case(addr) 2’d0: {a,b,c,d}={in,3’d0}; 2’d1:{a,b,c,d}={1’d0,in,2’d0}; 2’d2:{a,b,c,d}= {2’d0,in,1’d0}; 2’d3:{a,b,c,d}= {3’d0,in}; endcase end DEMUX

37. concatenation c 0000 a[3:0] b[2:0] data_in={a,b,4’d0,{3{c}}}; data_in[13:0] MEMORY

38. ModelingMuxes/Demuxes addr always@(*) begin case(addr) 2’d0: 2’d1: 2’d2: 2’d3: 0 0 0 endcase end

39. ModelingRegisters always@(posedgeclk) begin clk reset reg_out[N:0]

40. ArithmeticOperations a[N:0] b[N:0] c[N+1:0] Adder/ Subtracter cin add/sub saturate always@(*) begin c=a+b; end a[N:0] b[N:0] c[2N:0] Multiplier c=a-b; c=a*b; signed/unsigned saturate

41. Declarations reg [16:0]c; always@(*) c= a+b; wire[16:0]c; assign c= a+ b; a[15:0] b[15:0] Whatabouta&b? Shouldtheybe wireorreg? Adder c[16:0] always@(posedgeclk) c<=#1a+b;

42. VerilogCoding • MakeaDesignDiagram • Codeallthebuildingblocks • Namethewiresinthedesign diagram • Declarethemoduleportlist • Startcodingthelogicelements onebyone • DeclareVariables

43. modulecounter( input input input input clk, reset, increment, decrement, outputreg[3:0]count ); regenable; reg[3:0]mux_out; Example1:counter.v always@(*) enable=increment|decrement; always@(*) begin case(increment) 1’b0:mux_out= count-1; 1’b1:mux_out=count+1; endcase end always@(posedgeclk) if(reset) count<=#10; elseif(enable) count<=#1mux_out; endmodule dec_out inc_out ++ -- mux_out increment enable decrement count

44. Verilog LogicVerification

45. Generate Inputs ModuleUnder Test(DUT) DUTModel OR Reference Outputs Monitor Outputs == Monitor results TestBench

46. Example:TestBench forcounter counter.v

47. Example:TestBench forcounter moduletb_counter; regclk; regreset;regincrement; regdecrement; wire[3:0]count; countercounter_inst(

48. moduletb_counter; clkreset increment decrement xxxx count[3:0] 0000 000100100001 initial begin clk=0; forever #5clk= end Cstyleblock executing statements sequentially unlesswemove forwardintime axisusing# ,@(something), waitetc. ~clk; endmodule

49. moduletb_counter; clk reset increment decrement xxxx count[3:0] 0000 000100100001 Cstyleblock executing statements sequentially unlesswemove forwardintime axisusing# ,@(something), waitetc. endmodule

50. initial begin increment=0; decrement=0; reset=0; @(posedgeclk) reset<=#1 1; @(posedgeclk) reset<=#1 0; @(posedgeclk); #1increment= 1; repeat(2)@(posedgeclk); Cstyleblock executing statements sequentially unlesswemove forwardintime axisusing# ,@(something), waitetc. @(posedgeclk); #1decrement= 0; repeat(20)@(posedgeclk); $stop; end