DFT Compiler 1 2004.12

1. DFT Compiler 12004.12 • Synopsys Customer Education Services • 2005 Synopsys, Inc. All Rights Reserved Synopsys 30-I-011-SSG-007

2. Course Materials • Student Workbook • Lab Book • Reference Materials • Course Evaluations

3. Facilities Building Hours Phones Emergency Messages EXIT Restrooms Smoking Meals Recycling Please turn off cell phones and pagers

4. Workshop Prerequisites You should have experience in the following areas: • Digital IC design • Verilog or VHDL • UNIX and X-Windows • A Unix based text editor

5. Curriculum Flow Physical Compiler 1 The Power of Tcl3 workshopsat 3 skill levels The Power of Tcl3 workshopsat 3 skill levels The Power of Tcl3 workshopsat 3 skill levels Design Compiler 1 PrimeTime: Advanced STAConstraint Debugging PrimeTime 1 You are here PrimeTime: Signal Integrity DFT Compiler 1 ATPG with TetraMAX Astro 1 Astro XTalk

6. Target Audience SoC Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million gate SoCs, and export design files to ATPG and P&R tools.

7. Introductions • Name • Company • Job Responsibilities • EDA Experience • Main Goal(s) and Expectations for this Course

8. Galaxy™ Design Platform Synopsys Manufacturing Test Solution Design Services • Test Synthesis • DFT Compiler™, SoCBIST • Unified DFT synthesis, verification and test signoff • Significant test cost reduction Design Compiler Module Compiler DFT Compiler Power Compiler Design- Ware JupiterXT Milkyway • ATPG • TetraMAX® ATPG, DSMTest, TenX • Leading-edge ATPG with comprehensive support for delay related defects Physical Compiler Astro PrimeTime SI Star-RCXT Hercules Proteus

9. External DFT and ATPG Flows Which flow(s) do you use now or plan to use in the future?

10. 1-Pass Test Suite: Environment Overview Boundary Scan Netlist BSDL Test Vectors RTL Source Design Compiler/Physical Compiler Environment BSDCompiler IEEE-1149.1 DFTCompiler 1-Pass Test Synthesis Scan Design (Gates) Setup Info STIL File TetraMAX Environment TetraMAX ATPG Sequential Fault Simulator Bridging Faults IDDQ Transition Delay Path Delay

11. DFT Compiler TM1-Pass Scan Synthesis • RTL Rule Checking: In-depth testability analysis at RT Level: • Helps designers write “test-friendly” RTL • AutoFix: Automatic correction of scan DRC violations: • Removes unpredictability from back-end design process • DFT synthesis • Shadow LogicDFT synthesis • Scan Synthesis: Transparent scan implementation: • Seamlessly optimize all design constraints — timing, area, power and test(logicalandphysicaldomain) • Hierarchical Scan Synthesis:Leverage existing flows and test models to gain multi-million gate capacity and improved performance (logical and physical domain)

12. Top-Down Scan Insertion Flow

13. DFT Compiler Test-Ready or Unmapped Flow RTLSource Testability Reports Scan-inserted Design • Start point is RTL (unmapped) design • IDEAL starting point • 1-Pass Scan synthesis achieved by taking RTL directly to a scan synthesized design Test-Ready Flow DFT Compiler DFT synthesis, test drc, test coverage preview

14. DFT Compiler Mapped Flow Gate-LevelSource Testability Reports Scan-inserted Design • Start point is gate-level (mapped) design with no scan circuitry yet • DFT Compiler performs scan cellreplacement and scan chain synthesis Mapped Flow DFT Compiler DFT synthesis, test drc, test coverage preview

15. DFT Compiler Existing Scan Flow Gate-LevelSource Testability Reports Scan-inserted Design Existing Scan Flow • Start point is gate-level design that already includes scan cells and chains • DFT Compiler performs scan chain extraction & test DRCs in preparation for TetraMAX ATPG DFT Compiler DFT synthesis, test drc, test coverage preview

16. Bottom-Up Scan Insertion Flow

17. Methods for High Capacity Scan Synthesis DC PC • Unified Design Rule Checking (UDRC): • Uses TetraMAX DRC for consistency and faster runtime • Rapid Scan Synthesis (RSS): • Avoids “test uniquification” and just stitches the scan chains • Test Models, Interface Logic Models (ILMs) with Test Models: • Highly reduced scan models of gate-level designs • XG Mode • New DC/PC infrastructure increases capacity and reduces runtime DFT Compiler UDRC RSS Test Models ILMs DFT Compiler UDRC RSS ILMs DC-XG PC-XG

18. Workshop Goal Use DFT Compiler to check RTL and mapped designs for DFT violations, insert scan chains into very large multi-million gate designs in either logical or physical flows, and export all the required files for downstream tools.

19. Agenda DAY 2 4 3 DFTC User Interfaces DFT for Clocks and Resets Creating Test Protocols 1 1 Understanding Scan Testing

20. Workshop Objectives: Day 1 • Define the test protocol for a design • Perform DFT checks at both the RTL and gate-levels • State common clocking and reset/set design constructs that cause typical DFT violations • Automatically fix certain DFT violations at the gate-level using AutoFix

21. Agenda DAY 8 Top-Down Scan Insertion 2 5 6 7 DFT for Tristate Nets DFT for Bidirectional Pins DFT for Embedded Memories

22. Workshop Objectives: Day 2 • State design constructs that cause typical DFT violations and how you can workaround these problems: • Tristate nets • Bidirectional pins • Embedded memories • Insert scan to achieve well-balanced top-level scan chains and other scan design requirements

23. Agenda DAY 12 Conclusion 3 10 High Capacity DFT Flows 11 Test Data Volume Reduction 9 Exporting Design Files CS Customer Support

24. Workshop Objectives: Day 3 • Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route • Customize the test initialization sequence, if needed • Modify a bottom-up scan insertion script for full gate-level designs to use Test Models/ILMs with RSS and run it • Preview top-level chain balance using test models/ILMs after block level scan insertion and revise block level scan architecture as needed to improve top-level scan chain balance • Insert additional observe test points to reduce number of ATPG patterns

25. Icons Used in this Workshop Lab Exercise Caution Recommendation Definition of Acronyms Question For Further Reference “Under the Hood” Information Group Exercise

26. Test Automation Docs are on SolvNet!