1 / 5

Calorimeter Trigger+Readout Hardware in a uTCA Architecture -- Some Thoughts --

This document discusses the potential of a combined architecture for ECAL and HCAL in the challenges of SLHC, and the compatibility of the uTCA architecture with high-bandwidth, flexible interconnects. It also addresses legacy mismatch issues and the importance of clock, slow control, and fast control for SLHC.

frankriddle
Download Presentation

Calorimeter Trigger+Readout Hardware in a uTCA Architecture -- Some Thoughts --

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Calorimeter Trigger+Readout Hardware in a uTCA Architecture-- Some Thoughts -- Jeremiah Mans – University of Minnesota CMS SLHC Trigger Workshop – Nov 29, 2007

  2. Thoughts for Consideration • A combined architecture bringing together ECAL and HCAL early and performing local seeding should be very powerful for the challenges of SLHC • The uTCA architecture is a nice match to the needs for high-bandwidth, flexible interconnects. • LHC-specific issues: • Legacy links to front ends – some “suboptimal” choices were made in the original designs which we may have to live with • Fast controls and clock distribution are important for LHC SLHC Trigger Workshop -- Calo Readout+Trigger in uTCA

  3. Legacy mismatch • uTCA is designed for very high speed serial interconnects (2.5 Gbps data) • Existing ECAL and HCAL links are much slower (0.8 Gbps /1.2 Gbps) – with a symmetric system, we can’t feed in the data fast enough to keep the 2.5 Gbps links full (assuming 1-1 in/out) • Upgrades may be unlikely – difficulty and risk associated with complete detector disassembly (required for ECAL upgrade) • Ideal design for a receiver/calculator card should take into account the inherent asymmetry: more input links than output links for example SLHC Trigger Workshop -- Calo Readout+Trigger in uTCA

  4. Clock, Slow Control, Fast Control • Critical clocks • LHC Bunch Clock – for pipelined calculations • Deserializer reference clocks : current HCAL links require LHCx2 frequency reference • Fast control • TTC will hopefully be replaced by a higher-bandwidth trigger/fast control system for SLHC capable of transmitting more information (partial trigger mask?, data destination tag?, etc) • Future implementation (in the counting room) is likely to be based on firmware within FPGAs rather than new ASICs • Slow control via Ethernet – independence from custom bus adapters! SLHC Trigger Workshop -- Calo Readout+Trigger in uTCA

  5. Initial R&D Directions • Develop a clock-and-control receiver card • For the current version, use TTC as the fast control standard • Produce backplane clocks: LHC, 2xLHC (QPLL), crystal(?) • Possibly develop in MCH form-factor : also encorporate ethernet-switch chip • Free-toolchain for slow control development • Nice microcontrollers exist for Ethernet interface, but the development kit is rather expensive [should be relatively easy, since all toolchains seem to support gcc at the backend] • Goal: use vanilla uTCA as a starting point • We will probably want a custom backplane in the future, but if we stay compatible with the standard, we can easily test small systems, etc SLHC Trigger Workshop -- Calo Readout+Trigger in uTCA

More Related