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Intel Core 2 Duo. Hiep Hong CS 147 Spring 2009. CPU Chronology. CPU Chronology. Pre-Intel 8086:. Intel 4004 108 KHz 2300 transistors Intel 8008 500-800 KHz 3500 transistors Intel 8080 2 MHz 4500 transistors. CPU Chronology. CPU Chronology. CPU Chronology.

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Hiep hong cs 147 spring 2009

Intel Core 2 Duo

Hiep Hong

CS 147

Spring 2009



Cpu chronology1
CPU Chronology

Pre-Intel 8086:

Intel 4004

  • 108 KHz

  • 2300 transistors

    Intel 8008

  • 500-800 KHz

  • 3500 transistors

    Intel 8080

  • 2 MHz

  • 4500 transistors





Dual core or core 2 duo
Dual-Core or Core 2 Duo

  • Core 2 Duo is a brand name by Intel.

  • Dual-Core is a generic description meaning two separate physical cores in one chip package.

  • Example: Pentium Dual Core, Core Duo and Core 2 Duo.



Intel core 2 duo1
Intel Core 2 Duo

  • 64 bit computing.

  • x86-64 instruction set.

  • The second generation of dual-core processors from Intel.

  • Two independent processor cores.

  • Share up to 6MB of L2 cache.

  • Developed with a new Architecture called Core Microarchitacture.





Core m icroarchitecture
Core Microarchitecture


Core m icroarchitecture1
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced digital media boost.

  • Memory disambiguation.

  • Advanced power gating.


Core microarchitecture
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced digital media boost.

  • Memory disambiguation.

  • Advanced power gating.



Advanced smart cache continued
Advanced smart cache continued

  • If one core has minimal cache requirements, the other core can dynamically increase its share of L2 cache

  •  Reduce cache misses.

  •  Improve performance.


Core m icroarchitecture2
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced digital media boost.

  • Memory disambiguation.

  • Advanced power gating.




Macro fusion continued1
Macro-Fusion continued

  • Enable common pair of instructions to be combined into a single instruction during decoding.

  • Reduce the total of executed instructions.

  • Allow processor to execute more instructions in less time.

  • Increase performance.


Macro fusion continued2
Macro-Fusion continued

Without macro-fusion

With macro-fusion

1 load eax, [mem1]

2 cmp eax, [mem2]

3 jne target

1 load eax, [mem1]

2 cmp eax, [mem2] + jne target


Core m icroarchitecture3
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced digital media boost.

  • Memory disambiguation.

  • Advanced power gating.


Advanced digital media boost
Advanced Digital Media Boost

  • Improve performance when executing Streaming SIMD Extension (SSE, SSE2, SEE3) instructions.

  • Accelerate video, speech, image, speech and image, photo processing, encryption, financial, engineering and scientific applications.


Advanced digital media boost1
Advanced Digital Media Boost

128-bit Streaming SIMD Extension (SSE, SSE2, SEE3) instructions.


Core m icroarchitecture4
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced digital media boost.

  • Memory disambiguation.

  • Advanced power gating.


Memory disambiguation
Memory Disambiguation

  • Accelerate the execution of memory-related instructions.

  • Load data for instructions about to be executed before all previous store instructions were executed.

  • Memory-related instructions that can be executed out of order.




Core m icroarchitecture5
Core Microarchitecture

  • Advanced smart cache.

  • Macro-fusion.

  • Advanced Digital Media Boost.

  • Memory disambiguation.

  • Advanced power gating.





References
References

  • http://www.intel.com

  • http://wikipedia.org

  • http://www.zdnet.com