1 / 9

CPUz 4 n00bz

CPUz 4 n00bz. CPU Diagram. RAM (Memory). Control Unit (CU). Program Counter (PC). Cache. Address Bus. Instruction Register (IR). Decoder. Arithmetic Logic Unit (ALU). Data Bus. Accumulator. Additional CPU Components. Program counter (PC)

forbes
Download Presentation

CPUz 4 n00bz

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CPUz 4 n00bz

  2. CPU Diagram RAM (Memory) Control Unit (CU) Program Counter (PC) Cache Address Bus Instruction Register (IR) Decoder Arithmetic Logic Unit (ALU) Data Bus Accumulator

  3. Additional CPU Components • Program counter (PC) • Holds the address of the next instruction in the program sequence • Instruction register • Holds the operation code of the type of instruction to be executed (e.g. ADD, SUB) • Accumulator • ALU’s internal register that holds ongoing total

  4. Fetch-Execute Again • Fetch instruction from the address stored in the program counter • Store instruction in instruction register • Decode instruction register • Execute operation (control unit tells ALU what to do) • ALU performs operation and uses its accumulator to remember result • Store accumulator result back to memory

  5. What happens when we need to pause the fetch-execute cycle? • Interrupts! • Things that “interrupt” the processor’s normal operation • Handle events and exceptions • Keyboard input • Null pointer exception • etc. • Special code exists to handle instructions, which is also stored in RAM

  6. Interrupt Register • Stores the offset address of the special interrupt handling code • Interrupt Code Address = Base Address + Interrupt Register • Basically…it stores the location in memory of where you go to handle the interrupt

  7. Processor Optimizations • Pipelining • Fetch-execute cycle overlapping for multiple instructions

  8. Instruction Pipelining

  9. More Cool Optimizations • Multiprocessing • Dual-core and Quad-core processors • Cell processor has 8 processors! • http://upload.wikimedia.org/wikipedia/en/d/da/Cell_Broadband_Engine_Processor.jpg

More Related