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Troisième Partie Chapitre 5 Un Processeur à Registres

Troisième Partie Chapitre 5 Un Processeur à Registres. Block Diagram of RP1. A0. D0. IR. T1. T2. CU. A3. ALU. CC. SP. TP. PC. D7. +. 1. -. memory. Central Processing Unit. m 1 : t 1 : Ax => Ma , R t 2 : t w : ... t w : t 3 : Md => Dy m 2 :.

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Troisième Partie Chapitre 5 Un Processeur à Registres

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  1. Troisième Partie Chapitre 5 Un Processeur à Registres

  2. Block Diagram of RP1 A0 D0 IR T1 T2 CU A3 ALU CC SP TP PC D7 + 1 - memory Central Processing Unit

  3. m1 : t1 : Ax => Ma,R t2 : tw : ... tw : t3 : Md => Dy m2 : Memory access time Memory Cycle (Read)

  4. m1 : t1 : Ax => Ma, Dy => Md, W t2 : tw : ... tw : t3 : m2 : Memory access time Memory Cycle (Write)

  5. Data handling : ADD,Dx,Dy : Add contents of Dy to contents of Dx SUB,Dx,Dy : Subtract contents of Dy from contents of Dx MUL,Dx,Dy : Multiply contents of Dx by contents of Dy DIV,Dx,Dy : Divide contents of Dx by contents of Dy CMP,Dx,Dy : Compare contents of Dx and Dy, adjust Condition Code Registers accordingly. ADI,Rx,a : Add a constant to contents of Rx Register processorInstructions

  6. Data transfer : LDI,Rx,a : load a constant a into Rx. LOD,Rx,Ry : copy value from Ry into Rx. LOD,Dx,a : copy value from direct address into Dx STO,Dx,a : copy value from Dx into direct address. LOD,Dx,Ay,a : copy value from relative address into Dx STO,Dx,Ay,a : copy value from Dx into relative address. Stack processorInstructions

  7. Control : JMP,a : Jump to specified address in code JPZ,a : Jump if the Z condition code is set. JNZ,a : Jump if the Z condition code is clear. JPN,a : Jump if the N condition code is set. JNN,a : Jump if the N condition code is clear. JPV,a : Jump if the V condition code is set. … JSR,a : Call subroutine at specified address in code RET : Return from subroutine LNK,Ax : Establish dynamic link with Ax as base ULK,Ax : Restore previous environment using Ax HLT : Stop execution Stack processorInstructions

  8. m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR t4Ry > T1 t5T1 > Rx Data Move LOD Rx,Ry

  9. Data Handling ADD Dx,Dy m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR t4Dx > T1 t5Dy > T2,ALU+ m1 : t1PC > Ma,R t2Ma+1 > PC ,ALU > Dx

  10. Data Handling CMP Dx,Dy m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR t4Dx > T1 t5Dy > T2,ALU- m1 : t1PC > Ma,R t2Ma+1 > PC

  11. Data Transfer LDI Dx, #17 Immediate m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1PC > Ma,R t2Ma+1 > PC t3Md > Dx

  12. Data Transfer LOD Dx, addr Direct m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1PC > Ma,R t2Ma+1 > PC t3Md > TP m3 : t1TP > Ma,R t2 t3Md > Dx

  13. 3 b a a+3 a+3 (a+3)*b Compilation Pattern : expression x = (a+3) * b // a,b,x local variables Reverse polish notation : a 3 + b *, LOD, D0,a LDI, D1,3 ADD D0,D1 LOD D1,b MUL D0,D1 STO D0,x 1 2 3 4 D2 D1 1 2 D0 3 4

  14. Control Flow JMP a m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1PC > Ma,R t2Ma+1 > PC t3Md > TP m1 : t1TP > Ma,R t2Ma+1 > PC t3Md > IR

  15. Control Flow (2) JPC a jump conditional m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1PC > Ma,R t2Ma+1 > PC t3Md > TP m1 : t1 TRUETP > Ma,R FALSEPC > Ma,R t2Ma+1 > PC t3Md > IR

  16. Evaluate B FALSE TRUE B L1 S2 S1 L2 Compilation Pattern : IF if (B){S1}; else {S2}; Evaluate B * value of B is result of * ALU operation * TRUE = 1 ; FALSE = 0 JPZ L1 Code for S1 JMP L2 L1 :Code for S2 L2: ...

  17. Compilation Pattern : Loop while (B) do {S} ; L1 :Evaluate B * value of B is result of * ALU operation * TRUE = 1 ; FALSE = 0 JPZ L2 Code for S JMP L1 L2 : . . . L1 Evaluate B FALSE B TRUE S L2

  18. L1 S Evaluate B TRUE B FALSE Compilation Pattern : Loop do {S} while (B); L1 :Code for S Evaluate B * value of B is result of * ALU operation * TRUE = 1 ; FALSE = 0 JNZ L1 . . .

  19. Evaluate N and M a = N L2 FALSE a < M S a = a+1 L1 Compilation Pattern : Loop for (a = N;a <= M; a++) S; Evaluate M and store in D0 Evaluate N and store in D1 L2 CMP D1,D0 JPN L1 Code for S (D0,D1 not used) ADI D1,#1 JMP L2 L1:. . .

  20. empty STACK Control Flow (3) JSR a jump subroutine m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1PC > Ma,R t2Ma+1 > PC t3Md > TP t4SP > Ma t5Ma + 1 > SP m3 : t1SP > Ma, PC > Md,W t2 t3 m1 : t1TP > Ma,R t2Ma+1 > PC t3Md > IR SP

  21. Control Flow (4) RET return from subroutine m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR m2 : t1SP > Ma,R t2 Ma – 1 > SP t3Md > TP m1 : t1TP > Ma,R t2Ma+1 > PC t3Md > IR

  22. Growing stack Procedure Call . . . To be done explicitly by programmer Local Variables Static Link AFTER JSR Dynamic Link T = SP Return Address B = A4 BEFORE JSR . . .

  23. Dynamic Link Management (1) LNK Ax m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR t4SP > Ma t5Ma + 1 > SP m2 : t1SP > Ma, Ax > Md, W t2 Ma > Ax t3

  24. Dynamic Link Management (2) ULK Ax m1 : t1PC > Ma,R t2Ma+1 > PC t3Md > IR t4 Ax > T1 t5 T1 > SP m2 : t1SP > Ma,R t2 Ma – 1 > SP t3Md > Ax

  25. Procedure Call void P(); { }; … P(); ... . . . JSR P . . . SP P LNK A4 ADI SP,… . . . ULK A4 RET A4 . . .

  26. void P(); { }; … P(); ... Procedure Call . . . JSR P . . . SP P LNK A4 ADI SP,… . . . ULK A4 RET A4 R.A. . . .

  27. Procedure Call void P(); { }; … P(); ... . . . JSR P . . . SP P LNK A4 ADI SP,… . . . ULK A4 RET D.L. A4 R.A. . . .

  28. Procedure Call void P(); { }; … P(); ... . . . JSR P . . . SP P LNK A4 ADI SP,… . . . ULK A4 RET D.L. A4 R.A. . . .

  29. Procedure Call void P(); { }; … P(); ... . . . JSR P . . . SP P LNK A4 ADI SP,… . . . ULK A4 RET A4 R.A. . . .

  30. . . . JSR P . . . Procedure Call void P(); { }; … P(); ... SP P LNK A4 ADI SP,… . . . ULK A4 RET A4 . . .

  31. CCC abc CCC uvw Procedure Parameters Actual Parameters Formal Parameters DoCCC(abc) Subroutine DoCCC(xyz) CCC xyz End DoCCC DoCCC(uvw)

  32. Parameter Passing Data Memory Base Register Called Block Activation Record Static link Actual Parameters Remark: Simple values returned by functions are often stored in a data register rather than on the stack. Dynamic links Calling Block Activation Record

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