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COE 202: Digital Logic Design Sequential Circuits Part 3

Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324. COE 202: Digital Logic Design Sequential Circuits Part 3. Objectives. State Reduction and Assignment Design of Synchronous Sequential Circuits Procedure Examples. State Reduction.

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COE 202: Digital Logic Design Sequential Circuits Part 3

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  1. Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM 2009 COE 202: Digital Logic DesignSequential CircuitsPart 3

  2. Ahmad Almulhem, KFUPM 2009 Objectives • State Reduction and Assignment • Design of Synchronous Sequential Circuits • Procedure • Examples

  3. Ahmad Almulhem, KFUPM 2009 State Reduction • The process of reducing the number of states • It results in less Flip flops • It may increase the combinational logic!

  4. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Is it possible to reduce this FSM? • Notes: • we use letters to denote states rather than binary codes • we only consider input/output sequence and transitions

  5. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Step 1: get the state table

  6. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Step 1: get the state table • Step 2: find similar states • e and g are equivalent states • remove g and replace it with e

  7. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Step 1: get the state table • Step 2: find similar states • e and g are equivalent states • remove g and replace it with e

  8. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Step 1: get the state table • Step 2: find similar states • d and f are equivalent states • remove f and replace it with d

  9. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Step 1: get the state table • Step 2: find similar states • d and f are equivalent states • remove f and replace it with d

  10. Ahmad Almulhem, KFUPM 2009 State Reduction (Example) • Reduced FSM Verify sequence:

  11. Ahmad Almulhem, KFUPM 2009 State Assignmnet • State Assignment: Assign unique binary codes to the states • Example • Three Possible Assignments:

  12. Ahmad Almulhem, KFUPM 2009 Design of Synchronous Sequential Circuits • Obtain a state diagram • State reduction if necessary • Obtain State Table • State Assignment • Choose type of flip-flops • Use FF’s excitation table to complete the table • Derive state equations • Use K-Maps • Obtain the FF input equations and the output equations • Draw the circuit diagram

  13. Ahmad Almulhem, KFUPM 2009 Example 1 • Problem: Design of A Sequence Recognizer • Design a circuit that reads as inputs continuous bits, and generates an output of ‘1’ if the sequence (1011) is detected Y X Input 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0

  14. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) Sequence to be detected:1011 • Step1: State Diagram

  15. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) • Step 2: State Table OR

  16. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) Q: How many FF? log2(no. of states) • Step 2: State Table • state assignment

  17. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) • Step 2: State Table • choose FF • In this example, lets use JK–FF for A and D-FF for B

  18. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) D–FF excitation table • Step 2: State Table • complete state table • use excitation tables for JK–FF and D-FF Next State output JK–FF excitation table

  19. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) • Step 3: State Equations • use k-map • JA = BX’ • KA = BX + B’X’ • DB = X • Y = ABX’

  20. Ahmad Almulhem, KFUPM 2009 Example 1 (cont.) • Step 4: Draw Circuit • JA = BX’ • KA = BX + B’X’ • DB = X • Y = ABX’

  21. Ahmad Almulhem, KFUPM 2009 Example 2 Problem: Design of A 3-bit Counter Design a circuit that counts in binary form as follows 000, 001, 010, … 111, 000, 001, …

  22. Ahmad Almulhem, KFUPM 2009 Example 2 (cont.) • Step1: State Diagram • The outputs = the states • Where is the input? • What is the type of this sequential circuit?

  23. Ahmad Almulhem, KFUPM 2009 Example 2 (cont.) • Step2: State Table • No need for state assignment here

  24. Ahmad Almulhem, KFUPM 2009 Example 2 (cont.) T–FF excitation table • Step2: State Table • We choose T-FF

  25. Ahmad Almulhem, KFUPM 2009 Example 2 (cont.) • Step3: State Equations

  26. Ahmad Almulhem, KFUPM 2009 Example 2 (cont.) • Step4: Draw Circuit • TA0 = 1 • TA1 = A0 • TA2 = A1A0

  27. Ahmad Almulhem, KFUPM 2009 Example 3 Problem: Design of A Sequence Recognizer Design a Moore machine to detect the sequence (111). The circuit has one input (X) and one output (Z).

  28. Ahmad Almulhem, KFUPM 2009 Example 3 (cont.) Sequence to be detected:111 • Step1: State Diagram 0 1 S0/0 S1/0 S2/0 S3/1 1 1 1 0 0 0

  29. Ahmad Almulhem, KFUPM 2009 Example 3 (cont.) • Step2: State Table • Use binary encoding • Use JK-FF and D-FF 0 1 S0/0 S2/0 S3/1 S1/0 1 1 1 0 0 0

  30. Ahmad Almulhem, KFUPM 2009 Example 3 (cont.) • Step4: Draw Circuit • For step3, use k-maps as usual JA = XB KA = X’ DB = X(A+B) Z = A.B

  31. Ahmad Almulhem, KFUPM 2009 Example 3 (cont.) • Timing Diagram (verification) • Question: Does it detect 111 ?

  32. Ahmad Almulhem, KFUPM 2009 Example 4 • Problem: Design a traffic light controller for a 2-way intersection. In each way, there is a sensor and a light N W E S

  33. Ahmad Almulhem, KFUPM 2009 Example 4 (cont.) • Step1: State Diagram 11, 10 NS / 01 EW / 10 00, 01 00, 10 11, 01 • INPUTS • SensorsX1, X0 • X0: car coming on NS • X1 : car coming on EW • OUTPUTS • Light S1, S0 • S0 : NS is green • S1 : EW is green • STATES • NS: NS is green • EW: EW is green

  34. Ahmad Almulhem, KFUPM 2009 Example 4 (cont.) • Exercise: Complete the design using: • D-FF • JK-FF • T-FF

  35. Ahmad Almulhem, KFUPM 2009 Example 5 • Problem: Design Up/Down counter with Enable • Design a sequential circuit with two JK flip-flops A and B and two inputs X and E. If E = 0, the circuit remains in the same state, regardless of the input X. When E = 1 and X = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11, back to 00, and then repeats. When E = 1 and X = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01, back to 00 and then repeats.

  36. Ahmad Almulhem, KFUPM 2009 10 00 01 00 01 00 01 11 10 11 11 10 11 11 10 00 01 00 01 10 Example 5 (cont.)

  37. Ahmad Almulhem, KFUPM 2009 E X Y JB JA B A C C A’ B’ KB KA clock Example 5 (cont.) JA = BEX + B’EX’ KA = BEX + B’EX’ JB = E KB = E

  38. Ahmad Almulhem, KFUPM 2009 More Examples • More design examples can be found at • Homework 5 • Textbook • Course CD • Google

  39. Ahmad Almulhem, KFUPM 2009 Summary • To design a synchronous sequential circuit: • Obtain a state diagram • State reduction if necessary • Obtain State Table • State Assignment • Choose type of flip-flops • Use FF’s excitation table to complete the table • Derive state equations • Use K-Maps • Obtain the FF input equations and the output equations • Draw the circuit diagram

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