CE_18_1 (xFab xh018)

1. CE_18_1 (xFab xh018) Andrei Dorokhov Institut Pluridisciplinaire Hubert Curien (IPHC) Strasbourg, France Internal note, 1/03/2010 e-mail address: Andrei.Dorokhov@IReS.in2p3.fr

2. OUT3 OUT2 CE_18_1 layout, 5 melal layers 3300 um X 3180 um= 10.494 mm^2 64 64 OUT4 OUT1

3. CE_18_1 description • Chip has 4 quarters, each has one analog output, 64 columns and 64 rows (== 1 readout frame == 4096 pixels) • Each quarter has 4 sub-matrixes: 64 columns by 16 rows • power supply: vddor =+3.3V, vdd, vdda =+1.8V, bias currents for column and source follower • Clock, Start, GReset are digital 3.3V inputs • Each sub-matrix has separate bias for collection diodes and common bias (for one quarter) for the additional metal electrode • In total up to 16 different pixel designs can be implemented

4. Global reset continuously active (+3.3V): all pixels (including reset pixels) are put in self-biased mode. Start pulse set address position to (0,0), the output multiplexed to columns with Clock, raw by raw. Counter is circular, so after 4096 it is not necessary to Start again. • Global reset not active (0V): the reset for pixels active only first frame (4096 Clocks) after Start, each row (except the first which is always in reset state) is reset and readout immediately after, this gives calibration reference. For the subsequent frames reset is not active, so one can make CDS between current readout (s) and reference. • One can pulse Global reset to 3.3V during first 4096 clocks (defined by the start signal), and then readout pixels in subsequent frames. CE_18_1 readout modes

5. CE_18_1 pixel designs (*1) - >> RadTol design errors [1] B1DF : DIFF without NIMP or PIMP is not allowed (except qnva, nedia) [1] B2DF : DIFF crossing NTYPE_WELL or PTYPE_WELL edge is not allowed [1] B3DF : DIFF crossing NWELL edge is not allowed [1] B2GA : Illegal GATE construct