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FPPA Analog Output Buffer Modifications

FPPA Analog Output Buffer Modifications. Outline Status Slew Rate Bias lines disturbance Modifications New Output Buffer performances. Status : Remember. For each CFA. Status (1). Problems discovered in the FPPA2001 output buffer . Extrinsic problem.

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FPPA Analog Output Buffer Modifications

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  1. FPPA Analog Output Buffer Modifications Outline • Status • Slew Rate • Bias lines disturbance • Modifications • New Output Buffer performances P.Pangaud FPPA2001 2nd Design Review

  2. Status : Remember For each CFA P.Pangaud FPPA2001 2nd Design Review

  3. Status (1) Problems discovered in the FPPA2001 output buffer. • Extrinsic problem. • Faster slew-rate from FPU impose to increase slew-rate and improve stability. • Intrinsic problems. • Bad Slew rate in the PNP emitter follower of the input stage (PPbuffer cell). • Rise time variation versus amplitude. • Voltage variation on the bias lines nbias and pbias. • Oscillation during settling time. P.Pangaud FPPA2001 2nd Design Review

  4. Status (2) Faster signal from FPU (slew-rate enhanced) P.Pangaud FPPA2001 2nd Design Review

  5. Status (3) Slew-rate from FPU = 1000V/us P.Pangaud FPPA2001 2nd Design Review

  6. Status (4) Bad response of Output Buffer Consequently, bad settling time and bad resolution ( + a little oscillation) P.Pangaud FPPA2001 2nd Design Review

  7. Observed slew rate (3) (1) In + In - (2) Slew-Rate Input (1) NPN emitter follower output (2) PNP emitter follower output (3) Slowly slew-rate (the first branch has not enough current to drive the second branch) P.Pangaud FPPA2001 2nd Design Review

  8. Bias lines disturbance (3) (biasfpua) From bias generator Oscillation during settling time Oscillation during settling time (2) (1) PPbias (2) (3) Come from local bias generator (1) (3) (2) PPbuffer P.Pangaud FPPA2001 2nd Design Review

  9. Modifications To improve slew-rate and stability, we must modify local bias and buffer architecture Add 2 emitter followers in parallel for improving the slew rate Add extra vdda connection from bias generator Add 5K resistor Add a booster Add 5K resistor This lower the impedance of the bias lines mbias and pbias P.Pangaud FPPA2001 2nd Design Review

  10. More vias between M1 and M2 New cells Old PPbuffer layout New PPbuffer layout Layout Modifications Differential connections from Bias generator (between vdd and signal) Newcells New PPbias layout P.Pangaud FPPA2001 2nd Design Review

  11. New FPPA Analog Buffer Analysis P.Pangaud FPPA2001 2nd Design Review

  12. New Output Buffer performances (1) Accurate response with stable signal over 12 bits P.Pangaud FPPA2001 2nd Design Review

  13. New Output Buffer performances (2) AC response : - Bandwidth (-3dB) = 245 Mhz - Output noise (rms) = 147 uV • Transient response : • Power consumption : 140 mW • Time rise : 1.6 ns • - Time fall : 2 ns • - Delay : 1.8 ns • - Settling Time (0.1%) = 5.7 ns versus FPPA2000 FPPA2001 FPPA’s Global simulations (R + C parasitics) P.Pangaud FPPA2001 2nd Design Review

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