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Introduction. CEG 4131 Computer Architecture III Miodrag Bolic. Four levels of computer description. Gate level – Specify operations at the individual bit level – Gates are primitive elements – Very cumbersome to do manually (logic minimization, etc.) Register level

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introduction

Introduction

CEG 4131 Computer Architecture III

Miodrag Bolic

four levels of computer description
Four levels of computer description

Gate level

– Specify operations at the individual bit level

– Gates are primitive elements

– Very cumbersome to do manually (logicminimization, etc.)

Register level

– Specify internal operation of processor-levelcomponents at the word level

– Primitives:

» Registers

» Counters

» Memories

» ALUs

» Clocks

» Combinational logic

four levels of computer description1
Four levels of computer description

Processor level

– Architectural Features specified

» Interfaces

» Instruction sets

» Data Representation

– More detailed individual componentspecification

Global system structure

– Overall system structure is defined

– Major components identified

» Processors

» Control modules

» Memory modules

» Interconnection structure

– Mostly a static description -- “black box”approach

basic parallel techniques 1
Basic parallel techniques [1]
  • Pipelining (time)
    • a number of functional units are employed in sequence to perform a single computation
    • a number of steps for each computation
  • Replication (space)
    • a number of functional units perform computation simultaneously
      • more processors
      • more memory
      • more I/O
  • Replication at the following levels:
    • Processor (multiple functional units)
    • Chip (multiple processors and/or hardware blocks)
    • Board (multiple processors and/or hardware systems)
    • Multiple computers
course content interconnection networks
Course Content - Interconnection Networks
  • Topologies of static networks
    • fully connected,
    • rings, meshes,
    • torii,
    • hypercubes,
    • k-ary n-cubes
  • Dynamic networks
    • Buses
    • Multistage intercon. networks
    • Crossbar switch networks
course content shared memory arch
Course Content – Shared Memory Arch.
  • Shared memory models
    • Communication occurs implicitly as result of loads and stores
  • Cache coherence
  • Programming shared memory systems

Shared memory

Interconnectionnetwork

I/O1

I/On

PE1

PEn

Processors

course content message passing arch
Course Content – Message Passing Arch.
  • Message passing models
    • direct access only to private address space (local memory),
    • communication via explicit messages (send/receive)
  • Routing
  • Programming message passing systems
  • Easier to scale than shared memory systems

Interconnectionnetwork

PE1

PEn

M1

Mn

P1

Pn

what will you learn from labs
What will you learn from Labs?
  • New approaches to design from the system level perspective
    • System-on-chip architectures
    • Design using IP (Intellectual Property) cores
    • Configurable instruction set architectures
  • Altera tools
    • SOPC builder
    • NIOS IDE
system on chip architectures
System-on-chip architectures
  • Single-processor architectures
  • Multiprocessor architectures
  • Cache coherence solutions for multiprocessors

Nios Processor

Tri-State

Bridge

Tri-State

Bridge

Compact Flash PIOs

SDRAM

Controller

Address (32)

32-BitNiosProcessor

Read

Avalon Bus

Write

UART

Data In (32)

ROM(with Monitor)

General Purpose Timer

Periodic Timer

Data Out (32)

Reconfig PIO

IRQ

LED PIO

LCD PIO

7-SegmentLED PIO

Button PIO

IRQ #(6)

references
References
  • Desco Sima, Terence Fountain and Peter Kascuk, Advanced Computer Architectures – A Design Space Approach, Pearson, 1997.