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Embedded System Hardware. Embedded system hardware is frequently used in a loop ( „hardware in a loop“ ):. actuators. Why worry about energy and power?. Processing units. Need for efficiency (power + energy):.

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Embedded System Hardware


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    1. Embedded System Hardware • Embedded system hardware is frequently used in a loop(„hardware in a loop“): actuators

    2. Why worry about energy and power? Processing units • Need for efficiency (power + energy): „Power is considered as the most important constraint in embedded systems“[in: L. Eggermont (ed): Embedded Systems Roadmap 2002, STW] Current UMTS phones can hardly be operated for more than an hour, if data is being transmitted.[from a report of the Financial Times, Germany, on an analysis by Credit Suisse First Boston; http://www.ftd.de/tm/tk/9580232.html?nv=se]

    3. poor design generation techniques The energy/flexibility conflict- Intrinsic Power Efficiency - Operations/Watt[MOPS/mW] Ambient Intelligence 10 DSP-ASIPs hardwired (ASIC) 1 Processors Reconfigurable Computing µPs 0.1 0.01 Technology 1.0µ 0.5µ 0.25µ 0.13µ 0.07µ Necessary to optimize! [H. de Man, Keynote, DATE‘02;T. Claasen, ISSCC99]

    4. Power and energy are related to each other P E t In many cases, faster execution also means less energy, but the opposite may be true if power has to be increased to allow faster execution.

    5. Low Power vs. Low Energy Consumption • Minimizing the power consumption is important for • the design of the power supply • the design of voltage regulators • the dimensioning of interconnect • short term cooling • Minimizing the energy consumption is important because of • restricted availability of energy (mobile systems) • limited battery capacities (only slowly improving) • very high costs of energy (solar panels, in space) • cooling • high costs • limited space • dependability • long lifetimes, low temperatures

    6. Application Specific Circuits (ASICS)or Full Custom Circuits • Custom-designed circuits necessary if ultimate speed or energy efficiency is the goal and large numbers can be sold. • Approach suffers from long design times and high costs (e.g. Mill. $ mask costs). ASIC synthesis not covered in this course.

    7. Processors • Key requirements: • Energy-efficiency • Code-size efficiency:Memory is a scarce resource in embedded systems,in particular for„systems-on-a-chip'' (SoC). • Run-time efficiency At the chip level, embedded chips include micro-controllers and microprocessors.Micro-controllers are the true workhorses of the embedded family. Theyare the original ’embedded chips’ and include those first employed as controllersin elevators and thermostats [Ryan, 1995].

    8. New ideas can actually reduceenergy consumption Pentium Crusoe Running the same multimedia application. As published by Transmeta [www.transmeta.com]

    9. Dynamic power management (DPM) • RUN: operational • IDLE: a sw routine may stop the CPU when not in use, while monitoring interrupts • SLEEP: Shutdown of on-chip activity Example: STRONGARM SA1100 400mW RUN 10µs 90µs 160ms 10µs 90µs IDLE SLEEP 50mW 160µW

    10. Fundamentals of dynamic voltage scaling (DVS) Power consumption of CMOScircuits (ignoring leakage): Delay for CMOS circuits:  Decreasing Vdd reduces Pquadratically,while the run-time of algorithmsis only linearly increased(ignoring the effects of the memorysystem).

    11. Voltage scaling: Example Exploitation discussed in codesign chapter Vdd [Courtesy, Yasuura, 2000]

    12. Variable-voltage/frequency example: INTEL Xscale OS should schedule distribution of the energy budget. From Intel’s Web Site

    13. Code-size efficiency • CISC machines:RISC machines designed for run-time-,not for code-size-efficiency • Compression techniques: key idea

    14. 16-bit Thumb instr.ADD Rd #constant 001 10 Rd Constant majoropcode source=destination minoropcode zero extended 1110 001 01001 0 Rd 0 Rd 0000 Constant • Reduction to 65-70 % of original code size • 130% of ARM performance with 8/16 bit memory • 85% of ARM performance with 32-bit memory [ARM, R. Gupta] Code-size efficiency • Compression techniques (continued): • 2nd instruction set, z.B. ARM Thumb instruction set:

    15. Two-level control store concept(indirect addressing of instructions) For each instruction address, S contains table address of instruction. Each instruction pattern is stored only once, and not repeatedly stored for each instruction address for which it is needed. Similar to concept of colour lookup table. Can be extended to include subroutines in lookup table. Called nanoprogramming in the Motorola 68000. instructionaddress S << 32 bit table of used instructions 32 bit CPU

    16. D P a x x[j-i] a[i] AX AY MY MX Address- registersA0, A1, A2 ..i+1, j-i+1 MF AF +,-,.. * x[j-i]*a[i] +,- Address generation unit (AGU) AR yi-1[j] MR Run-time optimization: Domain-oriented architectures n-1 Application: y[j] = i=0 x[j-i]*a[i] i: 0i  n-1: yi[j] = yi-1[j] + x[j-i]*a[i] Architecture: Example: Data path ADSP210x - Parallelism - Dedicated registers MR:=0; A1:=1; A2:=n-2; MX:=x[n-1]; MY:=a[0];for ( j:=1 to n) {MR:=MR+MX*MY; MY:=a[A1]; MX:=x[A2]; A1++; A2--}

    17. Digital Signal Processing (DSP) Processors - Features (1) - • Multiply/accumulate(MAC)and zero-overhead loop (ZOL) instructions (as shown) • Heterogeneous registers (as shown) • Separate address generation units (AGUs)(as in ADSP 210x)

    18. Digital Signal Processing (DSP) Processors - Features (2) - sliding window • Modulo addressing:Am++  Am:=(Am+1) mod n(implements ring or circular buffer in memory) x t2 t1 t ..x[n-2]x[n-1]x[0]x[1].. ..x[n-3]x[n-2]x[n-1]x[n]x[1] Memory, t=t1 Memory, t2=t1+1

    19. Saturating arithmetic: returns largest/smallest number in case of over/underflowsExample:a 0111b + 1001standard wrap around arithmetic (1)0000saturating arithmetic 1111(a+b)/2: correct 1000 wrap around arithmetic 0000 saturating arithmetic + shifted 0111 Saturating arithmetic „almost correct“

    20. Fixed-point arithmetic Shifting required after multiplications and divisions in order to maintain binary point.

    21. Real-time capability • Timing behavior has to be predictableFeatures that cause problems: • Caches, in particular with difficult to predict replacement strategies • Unified caches (conflicts between instructions and data) • Pipelines with difficult to predict stall cycles ("bubbles") • Interrupts that are possible any time • Memory refreshes that are possible any time • Instructions that have data-dependent execution times • [Dagstuhl workshop on predictability, Nov. 17-19, 2003]

    22. D P AX AY MY MX Address- registersA0, A1, A2 .. MF AF +,-,.. * +,- Address generation unit (AGU) AR MR Multiple memory banks or memories Simplifies parallel fetches