DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING

1. DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING BARIS TASKIN and IVAN S. KOURTEV ISPD 2005 High Performance Integrated Circuit Design Lab. Department of Electrical and Computer Engineering

2. Outline • Background and Motivation • Topological Limitations on CSS • Experimental Results • Conclusions

3. Introduction • High-Performance IC • Clock skew scheduling • Target: Minimum clock period • Observe limitations • Theoretically

4. Research Objective Objective: Improve the efficiency and results of clock skew scheduling through systematic delay insertion • Reconvergent paths • Edge-sensitive circuits • Level-sensitive circuits

5. System Modeling • Local data path • Circuit graph

6. Timing Parameters

7. Flip-Flop Operation Positive edge-triggered

8. Latch Operation Positive level-sensitive

9. Time Borrowing Flip-Flop based Latch based

10. Clock Skew Tskew(i,f) = ti - tf Clock signal delay at the initial register Clock signal delay at the final register

11. Clock Skew Scheduling OUTPUT INPUT

12. CSS: Edge-Sensitive Zero clock skew Non-zero clock skew

13. Edge-Sensitive CSS Model 1 Linear Programming (LP) model 1: J. P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, Vol C-39, pp. 945-951, July 1990.

14. CSS for Level-Sensitive • Latch-based • Non-zero clock skew • Flip-flop-based • Zero clock skew

15. Level-Sensitive CSS Model 1 Linear Programming (LP) model 1: B. Taskin and I.S. Kourtev, Linearization of the Timing Analysis and Optimization Level-Sensitive Digital Synchronous Circuits, IEEE Transactions on VLSI, Vol 12, No 1, pp. 12-27, January 2004.

16. CSS Topological Limitations • Series of data paths • Small practical limitations on CSS • Data path cycles • Limit minimum clock period • Reconvergent paths • Unexplored • They do matter!

17. Linear Topology • Series of local data paths • Small practical limits for clock skew scheduling

18. Linear Topology Timing 1

19. Linear Topology Timing 2

20. Data Path Cycles • Defined for retiming • Limiting for clock skew scheduling

21. Data Path Cycles Timing

22. Reconvergent Paths • Common topology • Lower bound Tmin

23. Reconvergent Paths Timing

24. Delay Insertion • Add delays to some paths • Modify shortest and potentially longest path delays

25. Reconvergent Path Timing DI

26. I if m I if I if m M CSS-DI for Edge-Sensitive I if M

27. I if I if m I if M m I if M CSS-DI for Level-Sensitive

28. Implementation Highlights • Corner cases for delays • Stand-alone frameworks • Edge-sensitive • Level-sensitive • Reasonable run-times • Under 2 minutes with barrier optimizer

29. Edge-Sensitive Results

30. Level-Sensitive Results

31. Quantitative Summary • Delay insertion applicable to • 41% of edge-triggered ISCAS’89 circuits • 34% of the level-sensitive • Improvement over conventional CSS • 10% for edge-triggered (26% when applicable) • 9% for level-sensitive (27% when applicable)

32. Conclusions • Delay insertion to logic • Systematic • Requires topological analysis • Linear, cycle, reconvergent • Practical requirements • Design budget for delay insertion • Discrete delay values • Placement

33. DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING QUESTIONS?

34. Clock Period Minimization Problem - 1 • Objective function : min T • Problem variables • For each register Ri • Earliest/latest arrival times ai, Ai • Earliest/latest departure times di, Di • Clock signal delay ti

35. Clock Period Minimization Problem - 2 • Problem Parameters • For each register Ri • Clock-to-output delay DCQ • Data-to-output DDQ • Setup time Si • Hold time Hi • For each local data path Ri  Rj • Data propagation time DPif

36. Practical Causes of Clock Skew • Size Mismatches • Buffer Size, Interconnect length • Process Variations • Leff, Tox etc. • Temperature Gradients • Power Supply Voltage Drop