CSE 242A Integrated Circuit Layout Automation

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CSE 242A Integrated Circuit Layout Automation. Lecture: Partitioning Winter 2009 Chung-Kuan Cheng. Outlines. Motivations Formulations 2-way partitioning, multi-way partitioning, multilevel partitioning, replication cut, clustering. Net Modeling Algorithms

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CSE 242A Integrated Circuit Layout Automation

Lecture: Partitioning

Winter 2009

Chung-Kuan Cheng

Outlines
• Motivations
• Formulations
• 2-way partitioning, multi-way partitioning, multilevel partitioning, replication cut, clustering.
• Net Modeling
• Algorithms
• Optimal Methods: Special cases, branch and bound,
• Heuristic Methods: group migration, network flow, clustering, simulated annealing, genetic approaches
Motivation
• Huge designs
• 100 Millions Trans
• Design
• Analysis
• Engineering Change Orders
• Good partitioning makes difference on design quality
Motivation: Applications
• Physical Hierarchy
• Divide and Conquer
• Project decomposition
• Complexity reduction of each level
• Emulation
• Hardware & Software codesign
• Management design resource
Formulations:
• Two Way Partitioning
• Random two-way partition
• N-pin net to be cut

b

a

a

a

b

a

b

b

Min-Cut

s

t

Theorem:

There exists an optimal linear placement

s.t. X and are separated.

Trend:

Min-Cut
• Opt->Linear Placement
• Trend: X=V

S

S

Multi-Way Partitioning
• K-Way Partitioning

X1

X2

Xk

Multi-Level Partitioning
• K-Level Partitioning
• Li<= Xi<= Ui
• Min Connection Cost
• E(Ti) <= Ci
• External connection cost <= threshold at level i
Generic Binary Tree
• L <= Xi <=U
• Level of Node = longest path to leaves
• Connection cost of node i at level L
Replication Cut

X Y

R

Y

R

X

R

C(X,Y)+C(Y,X)+C(Y,R)+C(X,R)

Performance-Driven Partitioning
• Need an incremental timing analysis to reflect the performance fast
• Replication helps
Retiming (Pipelined process)
• Allocate one clock cycle for interpartition communication
• System performance is dominated by

Loops:

Clustering
• K-Way Partitioning
• K>>10
• Obj strongly depends on applications
• Performance driven
• Obj min max # cuts between registers
• Complexity reduction

Ei external connection

Ii internal connection

Net Modeling
• Shifting: For each shift, we update k, n-k. The cost of the net changes only when k = 0, 1 or n-k =0, 1
• Two pin net clique
• 2/k total weight k-1
• 1/(k-1) S.K.
Net Modeling: Loop Model
• Suppose relative positions of pins are given, we can use a loop model
• The model remains correct if any two adjacent (in order) pins swap
Optimal Methods: Branch & Bound

Prune the branches when size constraint is violated

Partial cost >= existing cost

For U=L=|V|/2

# combinations = |V| ! / (|V/2)! (|V|/2)!

With an elegant implementation |V| <= 60 is feasible

Optimal Methods: Serial & Parallel Graph
• Dynamic Programming on Series-Parallel graph G(V, E, s, t)
• C(a, i, j) a: s, t on different sides
• C(b, i, j) b: s, t on the left side, left side has i nodes, right side has j nodes
Optimal Methods: Serial & Parallel Graph (Cont)
• Dynamic Programming on Series-Parallel graph G(V, E, s, t)
• C(a, i, j) a: s, t on different sides
• C(b, i, j) b: s, t on the left side, left side has i nodes, right side has j nodes
Heuristic Methods
• Group Migration
• Kernighan & Lin
• Fiducccia-Matheyses
• Programming
• Network Flow
• Replication Cut
• Clustering
Group MigrationKermighan & Lin Bisection
• Cost Ci: change of #cuts by moving node i to the other side
• Heapsort nodes in each partition according to Ci

Repeat

Repeat

Choose among the top k the best pair to swap

Update the cost, lock the moved nodes

Until all nodes are locked

Find the best sequence to swap

Until no more improvement

Group Migration
• Hill climbing to jump over local optimal solutions.
• Locking mechanism to avoid repeated moves.
Fiduccia-Mattheyses
• No swapping, move a single node each time
• Replace the heap with an array

Move all nodes according to a single net

Adv: move more nodes a the same operation. Good for multi-way, hierarchical where cost function dominated by the way to handle the nets

Dis: Complicate

Simulated Annealing

s, nexts: configurations, T: real, count: integer

• Begin
• S= random initial configuration
• T=T0
• Repeat
• Count= 0
• Repeat
• Count= count+1
• Nexts= generate(s)
• If c(nexts)<= c(s) or f(c(s),c(nexts),T)> random(0,1)
• Then s= nexts
• Until equilibrium(count,s,T)
• T= update(T)
• Unitl frozen(T)
• End

R

R

R

S

T

S

T

S

T

Clustering (Performance-Driven)
• Cap <= 4
• Min delay
• Min #clusters
• Min #clusters, T>=delay
• Min delay #clusters <= C
• Min max #inputs, #cluster<= C
• Min #clusters, #inputs <= K
Clustering Heuristics
• Cluster during target operation
• Recursive partitioning (ratio cut) to find clusters.
• Then treat each cluster as a single node to perform partitioning.
Linear Placement Iteration
• Do linear placement
• Treat each cluster as a single node repeat linear placement
• Adv: Work on the right target
• Dis: Need an efficient & effective target operation
Max Pair
• Given pairing cost, find the best pair to cluster
• Treat each cluster as a single node. Repeat the process
• The cost function does not encourage the largest node pair with other nodes continuously.
Max Matching
• Match the n/2 pairs simultaneously
• Adv: max matching can be solved in polynomial operation optimally
• Dis: enforce unnatural pair to merge

C and f are merged because their choices are taken by others

Variations of cost function
• Similarity of signatures (Data Path)
• Bit #, pin sequence
• Control signal, function of gate
Research Directions

Layout Hierarchy

Logic Hierarchy

• Obj: min distortion, max performance
• Linkage between two: eg ECO revision
• Improvement of operations by exploring the given hierarchy