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Design and Implementation of Embedded Microprocessors

Design and Implementation of Embedded Microprocessors. National Cheng Kung University. Chung-Ho Chen 陳中和. Outline. Introduction Architecture overview ISA examples Instruction types Exceptions Below the ISA Abstraction Processor implementation models Verification . Computer Markets .

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Design and Implementation of Embedded Microprocessors

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  1. Design and Implementation of Embedded Microprocessors National Cheng Kung University Chung-Ho Chen 陳中和

  2. Outline • Introduction • Architecture overview • ISA examples • Instruction types • Exceptions • Below the ISA Abstraction • Processor implementation models • Verification

  3. Computer Markets • Desktop computing • Price performance • Servers • Availability • Scalability • Efficient throughput • Embedded computers • Real time performance (soft and hard) • Power and memory

  4. Embedded Processors • Microprocessor • Use the same logic to perform many different functions. • Simplify the design of families of products. • Microcontroller • Includes I/O devices , on-chip memory. • Digital signal processor (DSP) • Microprocessor optimized for digital signal processing.

  5. Microprocessors in Embedded Systems Products • 4-bit Microcontrollers : PIC • 8-bit Microprocessors and microcontrollers • Intel : 8042 , 8048 , 8051 families • Motorola : 6805 , 68HC11 families • 16-bit Microprocessors and microcontrollers • Intel, AMD : 80186 families • Motorola : 68300 families • NEC, Hitachi, Phillips • 32-bit Microprocessors and microcontrollers • ARM families, MIPSfamilies, • Intel x86 families, StrongARM, XScale, • Motorola 68k families (ColdFire families) , • IBM PowerPC families • HitachiSuperH families

  6. CPU Design • ISA (instruction set architecture) • Micro-architecture design • Simulations • Implementation tools • Soft IP core • Hard IP core • Verification • Development systems

  7. Architecture overview • MIPS • ARM

  8. Example: The MIPS32 4K® family

  9. Example:ARM9 Family

  10. Register Bank • ARM : 37 registers • 31 general-purpose registers • 6 status registers • MIPS : 35 registers • 32 general-purpose registers • 3 Special-Purpose Registers (PC, HI and LO) MIPS ARM

  11. MIPS 4Km Core Block Diagram

  12. ARM940T functional Block Diagram

  13. Pipeline

  14. ISA Example: ARM Register Briefs • ARM has 31 general-purpose 32-bit registers. Only 16 of them are visible, R0 to R15. • ARM has 6 Program status registers (PSR). • The 16 registers are User mode register. Only exception can change User mode to other processor mode. • R14 is Link register used for holding the address of next to a Branch and link. • R15 is program counter (PC). • PC points to instruction that is two instruction being executed (In EXE). • R13 is generally used as a Stack Pointer (SP). This is defined by the Software.

  15. ARM Instruction Set • Uniform and fixed-length instruction fields, to simplify instruction decode. • Conditional (predicated) instructions • Almost all ARM instructions contain a 4-bit condition field. • If the condition is met, then instruction is executed. Otherwise, it becomes a no-op. • Most data-processing instructions can update the four condition code flags inCPSR(Negative, Zero, Carry and oVerflow) according to their result.

  16. Condition Code

  17. Program status register • 4 condition code flags • (N, Z, C, V) flags：Negative, Zero, Carry, oVerflow • 1 sticky overflow flag • Q bit：DSP instruction overflow bit. • In E variants of ARM architecture 5 and above. • 2 interrupt disable bits • I bit：disable normal interrupt (IRQ) • F bit：disable fast interrupt (FIQ) • 1 bit which encodes whether ARM or Thumb instructions are being executed. • T bit

  18. Program status register (cont.) • 5 bits that encode the current processor mode. • M[4:0] are the mode bits.

  19. Privileged modes Exception modes User System Supervisor Abort Undefined Interrupt FIQ R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_fiq R9 R9 R9 R9 R9 R9 R9_fiq R10 R10 R10 R10 R10 R10 R10_fiq R11 R11 R11 R11 R11 R11 R11_fiq R12 R12 R12 R12 R12 R12 R12_fiq R13 R13 R13_svc R13_abt R13_und R13_irq R13_fiq R14 R14 R14_svc R14_abt R14_und R14_irq R14_fiq PC PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq Current (Saved) Program Status Register CPSR and SPSR

  20. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  21. cond Signed_immed_24 1 0 1 L Branch instructions • Branch instruction is provided with a 24-bit signed offset • The branch target address is calculated by: • Sign-extending the 24-bit signed(two’s complement) immediate to 32 bits. • Shifting the result left two bit. • Adding this to the contents of the PC, which contains the address of the branch instruction plus 8. Example: B loop, BL loop, BLE loop. • Implementation B{L}{<cond>} target address • If conditionpassed(cond) then If L==1 ; this is a jump and link operation LR = address of the instruction after the branch instruction PC = PC + (signextend(signed_immed_24) <<2) (The PC contains the branch instruction address + 8)

  22. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  23. Shifter operand S Rn Rd cond Data-processing instructions • Arithmetic/logic instructions • One operand is always a register. • The other is an immediate value of a register value that may be shifted or rotated. • Shifter amount is specified in immediate value or a register. Example: SUBS r8, r6, #240; r8 = r6 – 240, condition codes are updated. • Implementation SUB {cond}{S} <Rd>, <Rn>, <shifter_operand> If conditionpassed(cond) then Rd = Rn - shifter_operand If S == 1 and Rd = R15 then CPSR = SPSP else if S == 1 then N = Rd[31] Z = 1 if Rd == 0, else 0 C = NOT borrowfrom(Rn - shifter_operand) V = overflowfrom (Rn - shifter_operand)

  24. Data-processing instructions (cont.) • Arithmetic/logic instructions • SUB r11, r12, r3, ASR #5; • Second operand = r3/32, arithmetic shift right 5 bits. • SUBS r15, r6, #240; r8 = r6 – 240, condition codes are updated. This can implement JUMP instructions since PC = r15 • Implementation: forwarding check • Source operand, r12 and r3/32. Not r3 only!

  25. Data-processing instructions (cont.) • Comparison instructions • Similar to the arithmetic/logic instructions. • Do not write result into registers. • Always update the condition flags based on their results. • Multiply instructions • 32x32bits = 32 bits or 64 bits in two registers. • Can do an accumulate (plus) operation. • Zero counting instruction • Find the number of leading zero in a register and write the result into the destination register.

  26. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  27. Status register transfer instructions • These instructions transfer the contents of CPSR or an SPSR to or from a general-purpose register. • Writing to CPSR can • Set condition codes. • Set interrupt enable bits. • Set processor mode.

  28. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  29. Load/store instructions • Load/store to/from a register. • Memory address = Base (in a register) • Memory address = Base + offset (Pre-indexed) • Memory address = Base, Base = Base +offset (Post-indexed) (!) • Offset can be • An immediate value or • An index register (which can be shifted).

  30. Load/store instructions (cont.) • Load/store to/from a register. • LDRNE r3, [r5, #300]! • Conditionally load r3 from a word 300 bytes above the address in r5, and then increments r5 by 300. • STRB r0, [r3, -r8, ASR # 2] • Stores the least significant byte from r0 to the address equal to (r3 – r8/4)

  31. Loads with flexible offset • LDRNE r2, [r5,#960]! • Implementation: If NE (not equal), r2 = Mem[r5 + 960], r5 = r5 + 960 (writeback !). This is a word load. • This is pre-indexed offset form in which the offset (960) is applied to the value in Rn (r5) before the data transfer takes place. • Op{cond}{B} Rd, [Rn, FlexOffset]{!} • Flexoffset is applied to the value in Rn. Flexoffset can be • #expr: A constant between –4095 to + 4095. • {-}Rm{, shift operation}. . • If ! is present, the adjusted address is written back to the base register Rn after the transfer takes place.

  32. STRs with shifted flexible offset • STR r2, [r9, #constant] • Implementation: Mem[r9+ constant] = r2. Constant can be an expression in the range 0-4095. (212). • STRB r0, [r3, -r8, ASR, #2] • Implementation: Mem[r3 – r8/4] = r0[7:0]. This is a byte write (indicated by B). • Op{cond}{B} Rd, [Rn, FlexOffset]{!} • Rd = r0, Rn = r3 (base), Rm = r8, ASR = arithmetic shift right working on Rm. This is also the pre-indexed form (compute first). • FlexOffset : {-}Rm{, shift operation} • Other shift operators: • LSL n: logical shift left n bits. (0 <= n <=31) • LSR n: logical shift right n bits. (1 <= n <=32) • ROR n: Rotate right n bits. 1<= n =< 31. • RRX: Rotate right one bit, with extend.

  33. Load/store multiple registers • LDM and STM for load/store multiple registers. • LDMIA r8, {r0, r2, r9}; r0 = Mem[r8], r2 = Mem[r8+4], then r9 = Mem[r8+4]. • Form: op{Conditiona} mode Rn{!}, registerList{^} • Mode: • IA: Increment address after each transfer • Start address Rn • IB: Increment address before each transfer • Start address Rn +4 • DA: Decrement address after each transfer • DB: Decrement address before each transfer • FD: Full descending stack • ED: Empty descending stack • FA: Full ascending stack • EA: Empty ascending stack. H FDED Memory EA FA L

  34. Multiple Load/Store and stack • Load/store multiple in stack operation • Full stacks: Stack pointer points to the last used (full) location. • Empty stack: Stack pointer points to the first unused (empty) location. • Descending stack: Grow toward decreasing memory addresses. • Ascending stacks: Grow towards increasing memory addresses. • Thus, there are four types of stacks that can be defined: • Full descending, FD. • Empty descending, ED. • Full ascending, FA. • Empty ascending, EA.

  35. Swap register/memory contents • The ARM instruction set has two semaphore instructions: • Swap (SWP) • Swap Byte (SWPB) • Atomic update of semaphore operation. • These instructions are provided for process synchronization. • Example : SWPB R2. R1, [R0] • Load unsigned byte from mem[R0] into R2 • Store R1 into mem[R0] • Example : SWP R1, R1, [R2] • Exchange value in R1 and address R2

  36. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  37. Coprocessor instructions • ARM’s coprocessors have their own private register sets. ARM takes care of control flow. • There are three types of coprocessor instructions • Data processing instructions • Start a coprocessor-specific internal operation. E.g., floating point addition. ARM offers the instruction to its coprocessor. • Data transfer instructions • Load/store coprocessor registers form/to memory. The memory address is calculated by ARM by looking into the instruction. • Register transfer instructions • Transfer coprocessor register value form/to an ARM register.

  38. Instruction Type • Branch instructions • Data-processing instructions • Status register transfer instructions • Load and store instructions • Coprocessor instructions • Exception-generating instructions

  39. Exception-generating instructions • SWI : Software interrupt instructions • Cause a software interrupt exception to occur. • Make call to an operating system, to request an OS-defined service. • BKPT : Software breakpoint instructions • Cause an abort exception to occur. • If suitable debugger software is installed on the abort vector, an abort exception generated in this fashion is treated as a breakpoint.

  40. SWI Exception • Form: SWI{cond} immed_24 • Implementation If conditionpassed(cond) then R14_svc = address of next instruction after SWI SPSR_svc = CPSR ; enter supervisor mode CPSR[4:0] =0b10011 ; enter supervisor mode CPSR [5:7] = 0u1; execute in ARM state; disable normal int. if high vectors configured then PC = 0x FFFF008 else PC = 0x0000008 SWI exception handler can use • immed_24 in SWI or • R0 or any other registers to pass parameters to determine system service.

  41. Return from SWI • To return: MOVS PC, R14 • Copy R14_svc to PC, and restore CPSR from SPSR_svc. • Copy R14 in supervisor mode back to PC, and copy SPSR_svc back to CPSR.

  42. Exception Type • Exception vector address

  43. Exception Process • General process procedure • When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. R14_<exception_mode> = return address; SPSR_<exception mode> = CPSR; CPSR[4:0] = exception mode number; If <exception mode> == reset or FIQ then CPSR[6] = 1; /* disable fast interrupt * /* Else CPSR[6] is unchanged * CPSR[7] = 1; /* disable normal interrupt */ PC = exception vector address

  44. Reset • Implementation R14_svc = unpredictable value; SPSR_svc = unpredictable; CPSR[4:0] = 0b10011; /* Mode is supervisor. * / CPSR[I:F:T]=CPSR[7:6:5] = 110; /* Disable interrupts and execute ARM instructions */ If high vectors configured then PC = 0xFFFF0000 Else PC = 0x00000000. • The above actions are done in Hardware. This is how the processor fetches the first instruction. Set the program counter to one of the above values by checking the configuration pin.

  45. Fetch Abort • Instruction fetch memory abort • Prefetch abort • Instruction page fault, protection violations etc. • This is an instruction fetch memory abort activated by the fetching of an invalid instruction. This exception is signaled by the MMU memory system. If the instruction is not executed due to branch in the sequence, prefetch abort will be cancelled.

  46. Fetch Abort • Implementation R14_abt = address of the aborted instruction + 4; SPSR_abt = CPSR; CPSR[4:0] = 0b10111; /* Enter abort mode */ CPSR[5] = 0; /* Execute ARM instruction */ CPSR[6] = unchanged; CPSR[7] = 1; /* Disable normal interrupt */ If high vector configured then PC = 0xFFFF000C Else PC = 0x0000000C.

  47. Return From Fetch Abort • To return after the page fault is fixed, use • Subs PC, R14, #4; • Why? R14_abt = address of the aborted instruction + 4. So we need to minus 4 to re-fetching the aborted instruction. Note that SUBS also copies SPSR_abt to CPSR. This restores the original program status at the time this instruction fault occurs.

  48. Data Abort • Data abort • This is a data access memory abort activated by the accessing of an invalid data. • That is, execution of load/store instructions. • This exception is signaled by the MMU memory system.

  49. Data Abort • Implementation R14_abt = address of the aborted instruction + 8; SPSR_abt = CPSR; CPSR[4:0] = 0b10111; /* Enter abort mode */ CPSR[5] = 0; /* Execute ARM instruction */ CPSR[6] = unchanged; CPSR[7] = 1; /* Disable normal interrupt */ If high vector configured then PC = 0xFFFF0010 Else PC = 0x00000010.

  50. Data Abort is more complicated • the values left in the general registers: • If the instruction only loads one general-purpose register, the value in the register is unchanged. • If the instruction loads more than one general register, unpredictable values are left in the destination registers (except for the PC and the base register of the instruction). • If the faulting instructions loads coprocessor registers, unpredictable values are left in the destination registers.

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