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第 8 章 有限状态机设计

第 8 章 有限状态机设计. 设计实例. 设计要求. 在时分通信系统中，设计一个巴克码识别器，当串行数据流中出现1110010（七位巴克码）时，输出识别信号，保证时分通信系统中的帧同步。. 状态分析：. 根据设计要求，电路输入端 S_IN 输入为随机串行数据流，七位巴克码组为 1110010 ，为此可以选择 S0 ， S1 ， S2 ， S3 ， S4 ， S5 ， S6 共七个状态。当电路处于状态 S6 时如果接收到的数据流出现一个 ‘0’ 时状态转向 S0 ， 同时 FD 输出为 ‘1’ ，通信系统同步单元通过信号 FD 提取帧同步信号 。.

esteban-ivarra
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第 8 章 有限状态机设计

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  1. 第8章 有限状态机设计

  2. 设计实例 设计要求 在时分通信系统中，设计一个巴克码识别器，当串行数据流中出现1110010（七位巴克码）时，输出识别信号，保证时分通信系统中的帧同步。

  3. 状态分析： 根据设计要求，电路输入端S_IN输入为随机串行数据流，七位巴克码组为1110010，为此可以选择S0，S1，S2，S3，S4，S5，S6共七个状态。当电路处于状态S6时如果接收到的数据流出现一个‘0’时状态转向S0，同时FD输出为‘1’，通信系统同步单元通过信号FD提取帧同步信号 。

  4. 原始状态图

  5. 原始状态表：

  6. 简化后状态表：

  7. 简化后状态图

  8. 程序代码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CHK2 IS PORT(CLK, RESET: IN STD_LOGIC; S_IN: IN STD_LOGIC; FD: OUT STD_LOGIC); END CHK2; ARCHITECTURE a OF CHK2 IS TYPE STATE_TYPE IS (S0, S1, S2,S3,S4,S5,S6); SIGNAL state: STATE_TYPE; BEGIN PROCESS (CLK,RESET) BEGIN IF RESET= '1' THEN state <= S0; ELSIF CLK'EVENT AND CLK = '1' THEN CASE state IS WHEN S0 =>FD <='0'; IF S_IN='1' THEN state <= S1;ELSE STATE <= S0; END IF; WHEN S1 =>FD<='0'; IF S_IN='1' THEN state <=S2;ELSE STATE <=S0; END IF; 接下页

  9. 接上页WHEN S2 =>FD <='0'; IF S_IN='1' THEN state <=S3;ELSE STATE <= S0; END IF; WHEN S3 =>FD <='0'; IF S_IN='0' THEN state <=S4;ELSE STATE <= S3; END IF; WHEN S4 =>FD <='0'; IF S_IN='0' THEN state <=S5;ELSE STATE <= S1; END IF; WHEN S5 =>FD <='0'; IF S_IN='1' THEN state <=S6;ELSE STATE <= S0; END IF; WHEN S6 => IF S_IN='0' THEN state <=S0;FD <='1'; ELSE STATE <= S2; END IF; END CASE; END IF; END PROCESS; END a;

  10. 8.1 一般有限状态机的设计 8.1.1 用户自定义数据类型定义语句 TYPE语句用法如下： TYPE 数据类型名 IS 数据类型定义 OF 基本数据类型 ; 或 TYPE 数据类型名 IS 数据类型定义 ; 以下列出了两种不同的定义方式： TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ; TYPE week IS (sun，mon，tue，wed，thu，fri，sat) ;

  11. 8.1 一般有限状态机的设计 8.1.1 用户自定义数据类型定义语句 TYPE m_state IS ( st0，st1，st2，st3，st4，st5 ) ; SIGNAL present_state，next_state : m_state ; 布尔数据类型的定义语句是： TYPE BOOLEAN IS （FALSE，TRUE） ； TYPE my_logic IS ( '1' ，'Z' ，'U' ，'0' ) ; SIGNAL s1 : my_logic ; s1 <= 'Z' ;

  12. 8.1 一般有限状态机的设计 8.1.1 用户自定义数据类型定义语句 子类型SUBTYPE的语句格式如下： SUBTYPE 子类型名 IS 基本数据类型 RANGE 约束范围; SUBTYPE digits IS INTEGER RANGE 0 to 9 ;

  13. 8.1 一般有限状态机的设计 8.1.2 为什么要使用状态机  有限状态机克服了纯硬件数字系统顺序方式控制不灵活的缺点。  状态机的结构模式相对简单。  状态机容易构成性能良好的同步时序逻辑模块。  状态机的VHDL表述丰富多样。  在高速运算和控制方面，状态机更有其巨大的优势。  就可靠性而言，状态机的优势也是十分明显的。

  14. 8.1 一般有限状态机的设计 8.1.3 一般有限状态机的设计 1. 说明部分 ARCHITECTURE ...IS TYPE FSM_ST IS (s0，s1，s2，s3); SIGNAL current_state, next_state: FSM_ST; ... 2. 主控时序进程 图8-1一般状态机结构框图工作示意图

  15. 8.1.3 一般有限状态机的设计 3. 主控组合进程 控组合进程的任务是根据外部输入的控制信号（包括来自状态机外部的信号和来自状态机内部其它非主控的组合或时序进程的信号），或（和）当前状态的状态值确定下一状态（next_state）的取向，即next_state的取值内容，以及确定对外输出或对内部其它组合或时序进程输出控制信号的内容。

  16. 8.1.3 一般有限状态机的设计 4. 辅助进程 【例8-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 ); END s_machine; ARCHITECTURE behv OF s_machine IS TYPE FSM_ST IS (s0, s1, s2, s3); SIGNAL current_state, next_state: FSM_ST; BEGIN REG: PROCESS (reset,clk) BEGIN IF reset = '1' THEN current_state <= s0; ELSIF clk='1' AND clk'EVENT THEN current_state <= next_state; END IF; END PROCESS; COM:PROCESS(current_state, state_Inputs) 接下页

  17. 接上页 BEGIN CASE current_state IS WHEN s0 => comb_outputs<= 5; IF state_inputs = "00" THEN next_state<=s0; ELSE next_state<=s1; END IF; WHEN s1 => comb_outputs<= 8; IF state_inputs = "00" THEN next_state<=s1; ELSE next_state<=s2; END IF; WHEN s2 => comb_outputs<= 12; IF state_inputs = "11" THEN next_state <= s0; ELSE next_state <= s3; END IF; WHEN s3 => comb_outputs <= 14; IF state_inputs = "11" THEN next_state <= s3; ELSE next_state <= s0; END IF; END case; END PROCESS; END behv;

  18. 8.1.3 一般有限状态机的设计 4. 辅助进程 图8-2 例8-1状态机的工作时序图

  19. 8.2 Moore型有限状态机的设计 • 8.2.1 三进程有限状态机 表8-1 AD574逻辑控制真值表（X表示任意） CE CS RC K12/8 A0 工 作 状 态 0 X X X X 禁止 X 1 X X X 禁止 1 0 0 X 0 启动12位转换 1 0 0 X 1 启动8位转换 1 0 1 1 X 12位并行输出有效 1 0 1 0 0 高8位并行输出有效 1 0 1 0 1 低4位加上尾随4个0有效

  20. 8.2.1 三进程有限状态机 图8-3 AD574工作时序

  21. 8.2.1 三进程有限状态机 图8-4 AD574工作时序

  22. 8.2.1 三进程有限状态机 图8-5 采样状态机结构框图

  23. 8.2.1 三进程有限状态机 【例8-2】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT (D :IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK ,STATUS : IN STD_LOGIC;--状态机时钟CLK，AD574状态信号STATUS LOCK0 : OUT STD_LOGIC; --内部锁存信号LOCK的测试信号 CS,A0,RC,K12X8 : OUT STD_LOGIC; --AD574控制信号 Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); --锁存数据输出 END AD574; ARCHITECTURE behav OF AD574 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL current_state, next_state: states :=st0 ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; BEGIN K12X8 <= '1'; LOCK0 <= LOCK ; COM1: PROCESS(current_state,STATUS) --决定转换状态的进程 接下页

  24. 接上页 BEGIN CASE current_state IS WHEN st0 => next_state <= st1; WHEN st1 => next_state <= st2; WHEN st2 => IF (STATUS='1') THEN next_state <= st2; ELSE next_state <= st3; END IF ; WHEN st3=> next_state <= st4; WHEN st4=> next_state <= st0; WHEN OTHERS => next_state <= st0; END CASE ; END PROCESS COM1 ; COM2: PROCESS(current_state) --输出控制信号的进程 BEGIN CASE current_state IS WHEN st0=> CS<='1'; A0<='1';RC<='1';LOCK<='0'; --初始化 WHEN st1=> CS<='0'; A0<='0';RC<='0';LOCK<='0'; --启动12位转换 WHEN st2=> CS<='0'; A0<='0';RC<='0';LOCK<='0'; --等待转换 WHEN st3=> CS<='0'; A0<='0';RC<='1';LOCK<='0'; --12位并行输出有效 WHEN st4=> CS<='0'; A0<='0';RC<='1';LOCK<='1'; -- 锁存数据 WHEN OTHERS=>CS<='1'; A0<='1';RC<='1';LOCK<='0';--其它情况返回初始态 接下页

  25. 接上页 END CASE ; END PROCESS COM2 ; REG: PROCESS (CLK) -- 时序进程 BEGIN IF ( CLK'EVENT AND CLK='1') THEN current_state <= next_state; END IF; END PROCESS REG; LATCH1 : PROCESS (LOCK) -- 数据锁存器进程 BEGIN IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ; Q <= REGL; END behav;

  26. 8.2.1 三进程有限状态机 图8-6 AD574采样状态机工作时序

  27. 8.2.1 三进程有限状态机 【例8-3】 COM: PROCESS(current_state,STATUS) BEGIN CASE current_state IS WHEN st0=> next_state <= st1; CS<='1'; A0<='1';RC<='1';LOCK<='0'; WHEN st1=> next_state <= st2; CS<='0'; A0<='0';RC<='0';LOCK<='0'; WHEN st2 => IF (STATUS='1') THEN next_state <= st2; ELSE next_state <= st3; END IF ; CS<='0'; A0<='0';RC<='0';LOCK<='0'; WHEN st3=> next_state <= st4; CS<='0'; A0<='0';RC<='1';LOCK<='0'; WHEN st4=> next_state <= st0; CS<='0'; A0<='0';RC<='1';LOCK<='1'; WHEN OTHERS => next_state <= st0; END CASE ; END PROCESS COM ;

  28. FPGA/CPLD LOCK 状态机FSM PROCESS COM 组合进程 PROCESS REG 时序进程 current_state PROCESS LATCH 锁存器 next_state AD574 CLK CS A0 RC K12/8 STATUS D[11..0] 模拟信号输入 Q[11..0] 采样数据输出

  29. 状态机VHDL源程序 END IF ; WHEN st3=> CS<='0'; A0<='0'; RC<='1'; LOCK<='0'; next_state <= st4; WHEN st4=> CS<='0'; A0<=’1'; RC<='1'; LOCK<='1'; next_state <= st0; WHEN OTHERS => next_state <= st0; END CASE ; END PROCESS COM ; REG：PROCESS (CLK) BEGIN IF ( CLK'EVENT AND CLK='1') THEN current_state <= next_state; END IF; END PROCESS REG; LATCH：PROCESS (LOCK) BEGIN IF LOCK='1'AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS ; Q <= REGL; END behav; K12X8 <= ‘1’ ; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574 IS PORT(D :IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK ,STATUS : IN STD_LOGIC; CS,A0,RC,K12X8 : OUT STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); END AD574; ARCHITECTURE behav OF AD574 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL current_state, next_state: states ; SIGNAL REGL :STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; BEGIN COM:PROCESS(current_state,STATUS) BEGIN CASE current_state IS WHEN st0 => CS<='1'; A0<='0'; RC<='0'; LOCK<='0'; next_state <= st1; WHEN st1=> CS<='0'; A0<='0'; RC<='0'; LOCK<='0'; next_state <= st2; WHEN st2=> CS<='0'; A0<='0'; RC<='0'; LOCK<='0'; IF (STATUS='1') THEN next_state <= st2; ELSE next_state <= st3;

  30. 状态机RTL电路图

  31. 状态机工作时序图 状态2：等待

  32. 8.2.2 单进程Moore型有限状态机 【例8-4】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MOORE1 IS PORT (DATAIN :IN STD_LOGIC_VECTOR(1 DOWNTO 0); CLK,RST : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END MOORE1; ARCHITECTURE behav OF MOORE1 IS TYPE ST_TYPE IS (ST0, ST1, ST2, ST3,ST4); SIGNAL C_ST : ST_TYPE ; BEGIN PROCESS(CLK,RST) BEGIN IF RST ='1' THEN C_ST <= ST0 ; Q<= "0000" ; ELSIF CLK'EVENT AND CLK='1' THEN 接下页

  33. 接上页 CASE C_ST IS WHEN ST0 => IF DATAIN ="10" THEN C_ST <= ST1 ; ELSE C_ST <= ST0 ; END IF; Q <= "1001" ; WHEN ST1 => IF DATAIN ="11" THEN C_ST <= ST2 ; ELSE C_ST <= ST1 ;END IF; Q <= "0101" ; WHEN ST2 => IF DATAIN ="01" THEN C_ST <= ST3 ; ELSE C_ST <= ST0 ;END IF; Q <= "1100" ; WHEN ST3 => IF DATAIN ="00" THEN C_ST <= ST4 ; ELSE C_ST <= ST2 ;END IF; Q <= "0010" ; WHEN ST4 => IF DATAIN ="11" THEN C_ST <= ST0 ; ELSE C_ST <= ST3 ;END IF; Q <= "1001" ; WHEN OTHERS => C_ST <= ST0; END CASE; END IF; END PROCESS; END behav;

  34. 8.2.2 单进程Moore型有限状态机 图8-7 例8-4状态机综合后的RTL电路模块图

  35. 8.2.2 单进程Moore型有限状态机 图8-8 例8-4单进程状态机工作时序

  36. 8.2.2 单进程Moore型有限状态机 图8-9 对应于例8-4的2进程状态机工作时序图

  37. 8.3 Mealy型有限状态机的设计 【例8-5】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY1 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END MEALY1; ARCHITECTURE behav OF MEALY1 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; BEGIN COMREG : PROCESS(CLK,RESET) BEGIN --决定转换状态的进程 IF RESET ='1' THEN STX <= ST0; ELSIF CLK'EVENT AND CLK = '1' THEN 接下页

  38. CASE STX IS WHEN st0 => IF DATAIN = '1' THEN STX <= st1; END IF; WHEN st1 => IF DATAIN = '0' THEN STX <= st2; END IF; WHEN st2 => IF DATAIN = '1' THEN STX <= st3; END IF; WHEN st3=> IF DATAIN = '0' THEN STX <= st4; END IF; WHEN st4=> IF DATAIN = '1' THEN STX <= st0; END IF; WHEN OTHERS => STX <= st0; END CASE ; END IF; END PROCESS COMREG ; COM1: PROCESS(STX,DATAIN) BEGIN --输出控制信号的进程 CASE STX IS WHEN st0 => IF DATAIN = '1' THEN Q <= "10000" ; ELSE Q<="01010" ; END IF ; WHEN st1 => IF DATAIN = '0' THEN Q <= "10111" ; ELSE Q<="10100" ; END IF ; WHEN st2 => IF DATAIN = '1' THEN Q <= "10101" ; ELSE Q<="10011" ; END IF ; WHEN st3=> IF DATAIN = '0' THEN Q <= "11011" ; ELSE Q<="01001" ; END IF ;

  39. 接上页 WHEN st4=> IF DATAIN = '1' THEN Q <= "11101" ; ELSE Q<="01101" ; END IF ; WHEN OTHERS => Q<="00000" ; END CASE ; END PROCESS COM1 ; END behav; 图8-10 例8-5状态机工作时序图

  40. 【例8-6】 MEALY2 LIBRARY IEEE; --MEALY FSM USE IEEE.STD_LOGIC_1164.ALL; ENTITY MEALY2 IS PORT ( CLK ,DATAIN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END MEALY2; ARCHITECTURE behav OF MEALY2 IS TYPE states IS (st0, st1, st2, st3,st4); SIGNAL STX : states ; SIGNAL Q1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN COMREG : PROCESS(CLK,RESET) --决定转换状态的进程 BEGIN IF RESET ='1' THEN STX <= ST0; ELSIF CLK'EVENT AND CLK = '1' THEN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN STX <= st1; END IF; WHEN st1 => IF DATAIN = '0' THEN STX <= st2; END IF; WHEN st2 => IF DATAIN = '1' THEN STX <= st3; END IF; WHEN st3=> IF DATAIN = '0' THEN STX <= st4; END IF; WHEN st4=> IF DATAIN = '1' THEN STX <= st0; END IF; WHEN OTHERS => STX <= st0; END CASE ; 接下页

  41. END IF; END PROCESS COMREG ; COM1: PROCESS(STX,DATAIN,CLK) --输出控制信号的进程 VARIABLE Q2 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN CASE STX IS WHEN st0 => IF DATAIN = '1' THEN Q2 := "10000" ; ELSE Q2 := "01010" ; END IF ; WHEN st1 => IF DATAIN = '0' THEN Q2 := "10111" ; ELSE Q2:="10100" ; END IF ; WHEN st2 => IF DATAIN = '1' THEN Q2 := "10101" ; ELSE Q2:="10011" ; END IF ; WHEN st3=> IF DATAIN = '0' THEN Q2 := "11011" ; ELSE Q2:="01001" ; END IF ; WHEN st4=> IF DATAIN = '1' THEN Q2 := "11101" ; ELSE Q2:="01101" ; END IF ; WHEN OTHERS => Q2:="00000" ; END CASE ; 接下页

  42. 接上页 IF CLK'EVENT AND CLK = '1' THEN Q1<=Q2; END IF; END PROCESS COM1 ; Q <= Q1 ; END behav; 图8-11 例8-6状态机工作时序图

  43. 8.4 状态编码 8.4.1 状态位直接输出型编码 表8-2 控制信号状态编码表 每一位的编码值都赋予了实际的控制功能，即： CS = current_state（4） ； A0 = current_state（3） ； RC = current_state（2） ； LOCK = current_state（1） 。

  44. 【例8-7】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD574A IS PORT ( D : IN STD_LOGIC_VECTOR(11 DOWNTO 0); CLK ,STATUS : IN STD_LOGIC; OUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END AD574A; ARCHITECTURE behav OF AD574A IS SIGNAL current_state, next_state: STD_LOGIC_VECTOR(4 DOWNTO 0 ); CONSTANT st0 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "11100" ; CONSTANT st1 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001" ; CONSTANT st2 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000" ; CONSTANT st3 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00100" ; CONSTANT st4 : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00110" ; SIGNAL REGL : STD_LOGIC_VECTOR(11 DOWNTO 0); SIGNAL LK : STD_LOGIC; BEGIN COM1: PROCESS(current_state,STATUS) --决定转换状态的进程 接下页

  45. BEGIN CASE current_state IS WHEN st0 => next_state <= st1; WHEN st1 => next_state <= st2; WHEN st2 => IF (STATUS='1') THEN next_state <= st2; ELSE next_state <= st3; END IF ; WHEN st3=> next_state <= st4; WHEN st4=> next_state <= st0; WHEN OTHERS => next_state <= st0; END CASE ; OUT4 <= current_state(4 DOWNTO 1); END PROCESS COM1 ; REG: PROCESS (CLK) -- 时序进程 BEGIN IF ( CLK'EVENT AND CLK='1') THEN current_state <= next_state; END IF; END PROCESS REG; LK <= current_state(1) ; LATCH1 : PROCESS ( LK ) -- 数据锁存器进程 BEGIN IF LK='1' AND LK'EVENT THEN REGL <= D ; 接下页

  46. 接上页 END IF; END PROCESS ; Q <= REGL; END behav; 图8-12 例8-7状态机工作时序图

  47. 8.4.2 顺序编码 表8-3 编码方式 【例8-8】 ... SIGNAL CRURRENT_STATE,NEXT_STATE: STD_LOGIC_VECTOR(2 DOWNTO 0 ); CONSTANT ST0 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000" ; CONSTANT ST1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001" ; CONSTANT ST2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010" ; CONSTANT ST3 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011" ; CONSTANT ST4 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100" ;

  48. 8.4.3 一位热码编码（One-hot encoding） 状态机编码方式设置 图8-13 一位热码编码方式选择窗

  49. 8.5 状态机剩余状态处理 表8-4 剩余状态

  50. 【例8-9】 ... TYPE states IS (st0, st1,st2,st3，st4，st_ilg1，st_ilg2，st_ilg3); SIGNAL current_state, next_state: states; ... COM：PROCESS(current_state, state_Inputs) -- 组合逻辑进程 BEGIN CASE current_state IS -- 确定当前状态的状态值 ... WHEN OTHERS => next_state <= st0; END case; 【例8-10】 ... alarm <= (st0 AND (st1 OR st2 OR st3 OR st4 OR st5)) OR (st1 AND (st0 OR st2 OR st3 OR st4 OR st5)) OR (st2 AND (st0 OR st1 OR st3 OR st4 OR st5)) OR (st3 AND (st0 OR st1 OR st2 OR st4 OR st5)) OR (st4 AND (st0 OR st1 OR st2 OR st3 OR st5)) OR (st5 AND (st0 OR st1 OR st2 OR st3 OR st4)) ;

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