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System Verilog Testbench Language. David W. Smith Synopsys Scientist Synopsys, Inc. Sample SOC and Testbench. Synchronous Interface Boundaries. DUT. Testbench. 10/100M Ethernet. External Memory. APB. AHB. Ethernet MAC. Memory Controller. CPU Core. Ethernet MAC. 1Gb

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slide1

System Verilog

Testbench Language

David W. Smith

Synopsys Scientist

Synopsys, Inc.

sample soc and testbench
Sample SOC and Testbench

Synchronous

Interface Boundaries

DUT

Testbench

10/100M

Ethernet

External

Memory

APB

AHB

Ethernet

MAC

Memory

Controller

CPU

Core

Ethernet

MAC

1Gb

Ethernet

Serial

Ports

RS232 model

Ethernet

MAC

Parallel

Ports

1284

model

10Gb

Ethernet

Control

Logic

USB

Bluetooth

controller

Bluetooth

model

USB model

Proprietary

Bus Controller

Infrared

controller

Proprietary

model

IR device

model

PCI

Controller

Protocol Checkers

for Interface

PCI Model

David W. Smith

system with multiple soc s
System with Multiple SOC’s

Cache

Cache

Cache

AMBA

AMBA

AMBA

CPU

CPU

CPU

FPU

FPU

FPU

Mem

Mem

Mem

Packet Switched Bus

SOC 1

SOC 2

SOC 3

DUT

  • At System Level Problem is Exacerbated
  • Abstractions and Re-use are Necessary!

David W. Smith

testbench requirements
Testbench Requirements
  • Stimulus Generation
    • Directed, Random, ATPG, ...
  • Checkers
    • Data
    • Protocols
  • Structured Connection to Multiple Independent Interfaces
    • Interconnect
    • Clocking Domain
    • Protocol
  • Abstract Modeling
    • High-level data structures
    • Dynamic Memory
      • Memory Management
    • Re-entrant Processes
      • Inter-process Synchronization, Control, and Communication
    • Re-usability
  • Single language for design (HDL) and verification (HVL)  HDVL

David W. Smith

basic types
Basic Types
  • Strings
    • arbitrary and dynamic length
    • methods to manipulate and convert strings
    • operators for comparison, concatenation and replication
  • Associative arrays
    • Indexed by integer, string, or class
    • first(index), last(index), next(index), prev(index), delete(index), and exist(index) methods
  • Dynamic arrays
    • integer mem[*];
    • mem.size();
  • Linked Lists
    • doubly linked list of any data type
    • iterator, modification, access methods
  • Classes, Objects and Methods
    • Object Oriented
      • Encapsulation, Inheritance, and Polymorphism
    • Objects referenced with handles (Safe Pointers)

David W. Smith

random variables and constraints
Random Variables and Constraints

Test Scenarios

  • Valid Inputs Specified as Constraints
    • Declarative

Constraints

Constraints

Input Space

Design

Valid

  • Constraint Solver
  • Find solutions

David W. Smith

random variables and constraints7
Random Variables and Constraints
  • rand, randc, and constraint added to class definition

class Bus;

rand bit[15:0] addr;

rand bit[31:0] data;

constraint word_align { addr[1:0] == 2’b0; }

endclass

  • Generate 50 data and quad-aligned addresses

Bus bus = new;

repeat(50)

begin

integer result = bus.randomize();

end

David W. Smith

basic additions
Basic Additions
  • Wild card operators (=?= and !?=)
  • Pass by reference
  • Argument default values and pass by name
  • Alias for nets
    • Short nets in a module
  • Dynamic Memory
    • Objects, threads, strings, dynamic and associative arrays
    • Automatically Managed

Declaration: task tk( var int[1000:1] ar );

Use: tk( my_array ); // no & needed

Declaration: task foo( int j = 5, int k = 8 );

Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9));

David W. Smith

process control synchronization
Process Control/Synchronization

all

any

priority

none

3.0 process

  • Verilog thread support from fork…join with continuation when all threads complete
  • SV threads use fork…join with continuation control
    • all
    • any
    • none
  • Threads execute until a blocking statement
    • wait for event, mailbox, semaphore, variable change, ...
  • Enhanced events (value and duration, passed as arguments)
  • Threads are controlled by
    • $terminate
    • $wait_child
    • $suspend_thread
    • $exit

David W. Smith

clocking domain
Clocking Domain
  • A clocking domain defines a synchronous interface for testbench and properties
  • Every clocking domain has only one clock event
  • Sample and drive timing specified with respect to clock
  • A signal may appear in multiple clocking domains
    • Input - multiple samples
    • Output – default bus resolution
  • Clocking domain creates a scope

David W. Smith

synchronous interfaces clocking
Synchronous Interfaces: Clocking

device

clk

bus

enable

Synchronous

Interface

full

data[7:0]

empty

clocking bus @(posedge clk);

default input #1ns output #2ns;

input enable, full;

inout data;

output empty;

output #6ns reset = top.u1.reset;

endclocking

Clocking Event “clock”

Default I/O skew

Hierarchical signal

Override Output skew

Race-free cycle and transaction level abstraction

Testbench Uses:

bus.enable

bus.data

...

David W. Smith

testbench program block
Testbench Program Block
  • Purpose: contains testbench verification code
  • program is similar to a module
    • Only one implicit initial block
    • Special semantics
      • Execute in verification phase
      • design  clocking  verification  read_only

program name ( port_list );

declarations (class, type, function, clocking...)

statements

endprogram

David W. Smith

system verilog testbench
System Verilog Testbench

Testbench

Verification Extensions

Testbench Specific

Basic Types

Aliases

Clocking Domains

Random Constraints

Program Block

Process Control/Synchronization

References

David W. Smith