MIPS RISC: Basic block size = 5 to 6 instructions slt,bne(beq) pair accounts for about 5% of all instructions execute

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# MIPS RISC: Basic block size = 5 to 6 instructions slt,bne(beq) pair accounts for about 5% of all instructions execute - PowerPoint PPT Presentation

Energy Efficient Program Control. 6.893 project proposal 9-26-2000 Ronny Krashinsky and Mike Sung. Program = Computation (add, shift) + Data ( load, store) + Control ( branch, jump ). MIPS RISC: Basic block size = 5 to 6 instructions

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Energy Efficient

Program Control

6.893 project proposal

9-26-2000

Ronny Krashinsky and Mike Sung

Program = Computation (add, shift) + Data (load, store) +Control (branch, jump)

• MIPS RISC:
• Basic block size = 5 to 6 instructions
• slt,bne(beq) pair accounts for about 5% of all instructions executed [M. Hampton]

for(i=0; i<x; i++)

j += i<<1;

compare (32b)

register file write (32b) bne: register file read (2x32b)

compare (32b)

program counter update

slt \$rc \$ri \$rx

bne \$rc \$r0 L

sll \$rs \$ri 1

la \$btr L

slt \$c1 \$ri \$rx

b \$c1 (btr)

sll \$rs \$ri 1

compare (32b)

condition register write (1b) bne: condition register read (1b)

program counter update

• 1 bit register access for branch condition
• No branch address calculation inside loop
• Possible compact instruction encoding (16 bit)
• Branch resolution in decode stage (1bit check)
• Other Ideas:
• Boolean operations can also use 1 bit condition registers
• Alternative control mechanisms: auto-decrement, predication, condition codes
• Program control in alternative architectures: Vector, Data Flow, VLIW
• Plan:
• Profile benchmarks (ISA simulator)
• ISA development
• Compiler support (assembly file hacking)
• Micro-architectural implementation/simulation (SyCHOSys)
• Energy simulation (SyCHOSys)
• Analyze and iterate