1 / 24

Introduction to Programmable Logic

Introduction to Programmable Logic. FYSIKUM. Nordic detector school. FPGA introduction. Introduction to VHDL. Implementation design flow. FPGA Structure. Logic block. I/O block. Interconnects. FPGA Logic Block (idealized). 4-input look up table (LUT) implements combinatorial logic

enoonan
Download Presentation

Introduction to Programmable Logic

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Introduction to Programmable Logic FYSIKUM Nordic detector school FPGA introduction Introduction to VHDL Implementation design flow Digital Systemkonstruktion - 1

  2. FPGA Structure Logic block I/O block Interconnects Digital Systemkonstruktion - 1

  3. FPGA Logic Block (idealized) • 4-input look up table (LUT) • implements combinatorial logic • Register • optionally stores output of LUT Register MUX Digital Systemkonstruktion - 1

  4. Field-Programmable Gate Arrays • Xilinx Spartan-3 die image. Note the regularity Digital Systemkonstruktion - 1

  5. Other FPGA features: • Dedicated block memories • Dual-port static RAM • Digital clock management/synthesis • Dedicated multipliers • Important for digital signal processing • "Hard" CPU cores • Xilinx: PowerPC, ARM 9 • Altera: Nios (Stratix II) • Multi-Gbit transceivers Digital Systemkonstruktion - 1

  6. For this course: • Device: Xilinx FPGA (Spartan 3E) • Design language: VHDL • Simulation tool: Xilinx iSim • Implementation: Xilinx ISE • These are specific choices, but…. • Overall contents are similar to other environments • Not very difficult to transfer skills Digital Systemkonstruktion - 1

  7. VHDL introduction • VHSIC Hardware Description Language • (VHSIC: Very high speed integrated circuit) • Both concurrent and sequential operations • International standard (1987, 1993, 2002) • Pure language definition • Large standard, with multiple ways to code the same behavior Digital Systemkonstruktion - 1

  8. Design unit (library unit) Inputs/outputs (entity) • In most basic form, defines • Inputs/outputs (entity) • Function of unit (architecture) • Can be instantiated and connected together in higher level design units. Function (architecture) Digital Systemkonstruktion - 1

  9. VHDL design unit Package Shared definitions Optional Assign specific design entities or architecturesto be used in specific places Configuration Entity Inputs and outputs Architecture Description of design Process Sequential statements Digital Systemkonstruktion - 1

  10. A Y B SEL Multiplexer entity library ieee; use ieee.std_logic_1164.all; entity Mux is port( a: in std_logic; b: in std_logic; sel: in std_logic; y: out std_logic ); end Mux; no semicolonafter last port declaration! Direction Type Port name Digital Systemkonstruktion - 1

  11. A Y B SEL An architecture(many ways to do this) architecture arch3 of Mux is begin y <= a whensel='0' else b; end arch3; Digital Systemkonstruktion - 1

  12. A Y B SEL Complete design unit: -- -- A 2 input multiplexer circuit -- library ieee; use ieee.std_logic_1164.all; entity Mux is port( a: in std_logic; b: in std_logic; sel: in std_logic; y: out std_logic ); end Mux; architecture arch2 of Mux is begin y <= a whensel='0' else b; end arch2; Digital Systemkonstruktion - 1

  13. Xilinx design environment (ISE) So, how do you use it? Digital Systemkonstruktion - 1

  14. Create a new project Digital Systemkonstruktion - 1

  15. Select device, design flow Digital Systemkonstruktion - 1

  16. Create new source Click here Or right-click here for menu Digital Systemkonstruktion - 1

  17. New source options Digital Systemkonstruktion - 1

  18. Initial definitions Digital Systemkonstruktion - 1

  19. Edit sources Digital Systemkonstruktion - 1

  20. Target to your hardware Digital Systemkonstruktion - 1

  21. Define constraints In this case, only I/O needsto be declared. More complexdesigns also need info ontiming constraints Digital Systemkonstruktion - 1

  22. User Constraint File (UCF) Digital Systemkonstruktion - 1

  23. Implement the design ISE follows thedesign flow up to the selected point. Digital Systemkonstruktion - 1

  24. Configure the FPGA Digital Systemkonstruktion - 1

More Related