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The NA62 Gigatracker

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  1. The NA62 Gigatracker presented by A. Kluge CERN/PH-ESE June 10, 2010 A. Klugea, G. AglieriRinellaa, V. Carassitic , A. Ceccucci, E. Cortina, J. Daguin, G. Dellacasab, M. Fiorinia, S. Garbolinb, P. Jarrona, J. Kaplona, F. Marchettob, E. Martina,d, A. Mapellia,e, G. Mazzab, M. Morela, M. Noya, G. Nüssle, P. Petagna, L. Perktolda, A. Cotta Ramusinoc, P. Riedlera, A. Rivettib, R. Wheadonb a CERN, Geneva Switzerland, bINFN Torino, Italy, cINFN Ferrara, Italy, dUCL Louvain la Neuve, Belgium, dEPFL LausanneSwitzerland

  2. Outline • NA62, introduction, challenge • GigaTracker • specifications, module, beam/data rate • electronics architecture • demonstrator ASICs • cooling • Summary A. Kluge

  3. NA62 - Introduction A. Kluge

  4. Experimental setup- NA62 hit correlation via matching of arrival times – 100 ps selects particleswith 75 GeV/c GTK seesall particles straw chambers measure position RICH identifies pions Mag2 Mag3 seeskaons only straw chambers RICH A. Kluge GTK3 GTK1 Cedar GTK2 Achromat Mag1 Mag4 250 m Vacuum tank beam: hadrons, only 6%kaons-> only 20% of charged kaon decay in the vacuum tank-> out of which only 10-11 decays are of interest (pion-neutrino-antineutrino) A. Kluge

  5. Experimental setup- NA62 beam: hadrons, only 6%kaons -> 0.06 only 20% of charged kaon decay in the vacuum tank -> 0.20 out of which only 10-11 decays are of interest -> 10-11decay into one pion, one neutrino and one anti-neutrino ______________________________________________________________________________ total probability1.2 x 10-13 • 100 events of kaon -> pion/neutrino/antineutrinoany deviation from standard model -> new physics A. Kluge

  6. Experimental setup: GTK specifications 200 ps per station 300 µm 100 pstime binning of arrival time 300 µm 800 MHz particle rate A. Kluge

  7. Experimental setup: GTK specifications 300 µm thin, 200µm sensor + 100 µm chip(<0.5% of X0), operated in vacuum 100 pstime resolution arrival time 300 µm A. Kluge

  8. Beam & detector configuration A. Kluge

  9. Beam profile 60 mm 27 mm A. Kluge

  10. ASIC covering beam 60 mm 12 mm 4.5-6 mm 13.5 mm 27 mm 45 rows times 40 columns per chip = 1800 pixels per chip A. Kluge

  11. Configuration for beam 27-60 A. Kluge

  12. Giga Tracker setup • Sensor&bonds: 0.24% X0(200 µm Silicon) • RO chip: 0.11% X0(100 µm Silicon) • Structure: 0.10% X0(100 µm Carbon or silicon) • Total: 0.45% X0 uniform A. Kluge

  13. The electronics specification A. Kluge

  14. General: System Specifications A. Kluge

  15. General: System Specifications A. Kluge

  16. The ASIC architecture A. Kluge

  17. Jitter-free pixel signal to TDC in EOC amplifier & discriminator/time-walk-compensator reference clock time-to-digital converter TDC buffering & read-out processor A. Kluge

  18. Precise clock signal to all pixels amplifier & discriminator/ time-walk-compensator& buffering & TDC reference clock buffering & read-out processor A. Kluge

  19. TDC per pixel architecture A. Kluge

  20. The time-to-digital conversion Dual slope TDC A. Kluge

  21. TDC Wilkinson (dual slope) t0= ntclkk2 / k1 t1 t2 U1 k1 k2 0 1 .. n-1 n t0 tclk tclk A. Kluge

  22. time walk A. Kluge

  23. Constant fraction discriminator ta,trailing tb,trailing A. Kluge

  24. End-of-column architecture A. Kluge

  25. The time-to-digital conversion Delay locked loop based TDC A. Kluge

  26. DLL based TDC Pixel cell DAC1 Ref CLK Phase detector & charge pump UP VCTRL PD CP 0 1 2 m-2 m-1 DOWN DLL CLK Clk = tclk TDC A. Kluge

  27. time walk A. Kluge

  28. t2 time-over-threshold A A1 t12 t1clk t t0 t1 tclk A. Kluge

  29. t2 Time-over-threshold A Sb A1 t12 t1clk t t0 t1 tclk A. Kluge

  30. Demonstrator A. Kluge

  31. Demonstrator • On-pixeldual slope TDC with CFD time walk compensation • End-of-columnDLL based TDC with time-over-threshold compensation • 2 demonstrator ASICs • 45 pixel - folded column with full frontend • complete TDC system • reduced read-out and formatting functionality A. Kluge

  32. TDC per pixel architecture A. Kluge

  33. On pixel cell TDC A. Kluge

  34. Layout – on pixel TDC 130µm A. Kluge

  35. Efficiency and calibration A. Kluge

  36. Preliminary pTDC jitter Promising test results A. Kluge

  37. EOC column architecture A. Kluge

  38. 45 45 45 45 45 40 Hit Arbiter Hit Arbiter Hit Arbiter Hit Arbiter Addr. Addr. Addr. Addr. 32 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 Hit Reg2 Hit Reg1 LVDS Ref CLK 320MHz DLL Digital processing serializer 45 x 40 pixel final chip

  39. 45 x 1 demonstrator 45 45 Hit Arbiter Addr. 32 Hit Reg2 Hit Reg1 LVDS Ref CLK 320MHz DLL Digital processing serializer

  40. GTK demonstrator ASIC A. Kluge

  41. T1, T2 versus input charge A. Kluge

  42. T1 jitter over input charge 40 – 55 ps 2.4 fC most probable charge A. Kluge

  43. TDC differential/integral non-linearity jitter on TDC 7 ps A. Kluge

  44. Full chain T1 jitter over input charge @ 0.7 fC threshold full chain: preamplifier discriminator transmission line TDC read-out 55 ps for full chain A. Kluge

  45. Full chain T1 rms jitter over pixel position no degradation because of long distance between pixel and TDC A. Kluge

  46. GTK cooling & electro-mechanical integration A. Kluge

  47. Giga Tracker setup • Sensor&bonds: 0.24% X0(200 µm Silicon) • RO chip: 0.11% X0(100 µm Silicon) • Structure: 0.10% X0(100 µm Carbon fiber) • Total: 0.45% X0 uniform • Readoutchip (12 x 20 mm), power < 3.2W per chip(2 W/cm2) • Vaccuum • Radiation • max. Temperature: 5 degree C,aimingfor -20 degree C A. Kluge

  48. Coolingsystemsunderinvestigation • carbonplate, conductivecooling • microchannels • convectivecooling in a vessel

  49. µ channel cooling A. Kluge

  50. Micro channel cooling Si: 31 x 31 x 1 mm3 surface roughness 160 nm 134 parallel channels: l = 20 mm, w = 67 µm, h = 680 µm, separation 92 µm 255 W/cm2 A. Kluge