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Terminations

Terminations. Chris Allen (callen@eecs.ku.edu) Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm. Termination resistors. Purpose Reduce transmission-line reflections Complete circuit for ECL and GaAs outputs Issues Reflection characteristics Current / power loading

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Terminations

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  1. Terminations Chris Allen (callen@eecs.ku.edu) Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm

  2. Termination resistors • Purpose • Reduce transmission-line reflections • Complete circuit for ECL and GaAs outputs • Issues • Reflection characteristics • Current / power loading • Component placement / routing issues • Resistor type, packaging • Options • End termination (L  0) • Source termination (S  0) • Other termination schemes • Differential line termination

  3. End termination • ECL output driver can sink/source 50 mA • GaAs (GigaBit Logic) can sink/source 60 mA • both could drive two 50- loads

  4. End termination • Fanout – How many inputs can one driver support? • not limited by the input current ( 500 A) per input  current available is 50 mA – 24 mA = 26 mA driver output term available based on this analysis ECL or GaAs could drive over 50 inputs 26 mA / 0.5 mA = 52 inputs • instead fanout is limited by the capacitance (3 pF to 5 pF per input) maximum fanout is about 10 inputs capacitance slow the signal rise time (RC circuit) rise time of RC circuit is,

  5. End termination • Daisy-chain layout – one termination (only) at the far end • Issues – stub connections to inputs must be short (> l / 6)so that each gate input appears as an open circuit

  6. End termination • Daisy-chain layout • termination resistor should be at the far end of the transmission line to minimize reflections or

  7. End termination • Alternative layout option with end termination • The driver ‘sees’ a single 50- transmission line that is properly terminated • The challenge is fabricating 100- lines • For CMOS and TTL technology • A 50- termination may exceed the driver’s current capacity • To accommodate CMOS and TTL, can increase Zo and R so that the current required is within the driver’s ability • Also, can reduce power dissipation in termination resistor with AC coupling • During transient (Tr), capacitor looks like short circuit Xc = Tr/Cif Xc << RT, then reflection is small

  8. End termination • Similar approach could also be used with ECL / GaAs • Reduce power dissipation in termination resistor with AC coupling • For differential lines in CMOS and TTL technology • The termination pair could be capacitively coupled, taking advantage of the inherent DC-balance R1 = 50  R1 + R2 >> 50 

  9. Source termination • Source (or series) termination (S = 0) • Another approach to reduce reflections is to focus on the source end Assumption – far end impedance, ZL >> Zo (~ open circuit)  L ~ 1 • For RO + RS = Zo, S = 0 RO is driver resistance • Issues – • Only valid for driving far-endload (intermediate positionsdo not see full transitionin single step) no daisy chaining

  10. Source termination • What is the driver’s output impedance? (CMOS, TTL, ECL, GaAs) • Digital circuit output stages have output resistances that depend on logic state

  11. Source termination • Why aren’t Ro(LO) higher for ECL and GaAs? Output transistor is not biased to cutoff mode Ro ~ 1/slope ~ 60  ~ 600 

  12. Source termination • Equivalent circuit for analyzing output • For RO(HI) RO(LO) • cannot find RS that • Satisfy • RO + RS = ZO for both HI and LO cases • For Zo = 50 , CMOS Rs ~ 30  ECL Rs ~ 40  GaAs Rs ~ 40 (but a big S when LO) • However to pull down the output for ECL and GaAs, a pull-down resistor is needed as well

  13. Source termination • How to determine value for Rpd? • First, find the current, Ipd, required to pull the voltage level down on the transmission line when the output goes low • V ~ 1 V  1 V/(2  50 ) = 10 mA  Ipd  10 mA • Second, during HI to LO transition, think of the trace as a charged capacitor • Enforce these two conditions for VOH = -0.8 V, VEE = -5 VRs = 40 , Zo = 50  2 Zo due to open transmission line (L = +1) Rpd 330 

  14. Source termination • Disadvantages of source termination • The source termination scheme produces the desired output voltage only at the far end of the transmission line • Therefore daisy-chaining is not permitted since gates attached midline will see irregular waveforms • Therefore all receiving gates must be clustered at the end of the line

  15. Source termination • Can drive more than one series terminated line, however must not exceed the max output current limit • Driving two or more lines required a lower pull-down resistor value • Drawing more quiescent current through the termination (IOH) reduces VOH (due to the gate’s internal resistance) resulting in a decreased noise margin

  16. Source termination • Alternatively could use a circuit with multiple outputs, e.g., a fanout buffer, to drive more than one series terminated line • Each output treated individually Load distribution Line impedance Pull-down resistor value

  17. Other termination challenges • When there are several signal drivers on a given transmission line and they are not located together, where should the termination be located ? • Example, TTL or CMOS tri-state outputs on bus, or ECL (or GaAs) gates connected in Wired-OR configuration on a transmission line • Possible solutions include: • Adding a source termination to each driver • Adding an end termination to each receiver • Adding a series resistance between every junction of branches • Adding a shunt termination in the middle of the network • Issues Option 1 well defined, requires little power, provides damping, reduces settling time Option 2 requires a lot of drive power but works in star configuration Options 1 and 2 provides a perfect solution except it wastes power and attenuates the signal Option 3 attenuates the signal at each junction  Option 4 is the middle termination

  18. Other termination challenges • Driving multiple lines with single source, single termination • Can drive a mix of terminatedand unterminated lines • Distorted waveforms result as the unterminated stub length increases • The ripple following the LO HItransition is a result of inadequate quiescent IOH level to cause a fullsignal level on all lines

  19. Other termination challenges • Data busing involves connecting two or more outputs and one or more inputs to the same signal line • Any driver can be enabled to apply data to the line • Termination resistors matching the line impedance connected to both ends to prevent reflections • In analyzing such a configuration, the capacitance of a disabled (unactive) driver should be taken as 2 pF for ECL

  20. Other termination challenges • Examples of how to terminate twisted pair cables

  21. Other termination challenges • Examples of how to terminate coaxial cables

  22. Termination resistor specifications • Accuracy • R = Rnom R (%), R is the tolerance • Impacts the reflection coefficient, • Variations in R and Zo affect  • Ideally R = 0 • Typical choices are 10%, 5%, 1% • Recall   noise marginfor ECL, NM ~ 15% for R  10%  Zo +22% or -19% for R  5%  Zo +28% or -22% for R  1%  Zo +34% or -25% for R  0%  Zo +35% or -26% Zo impacts board manufacturing tolerances

  23. Termination resistor specifications • Power rating • Found using worst case condition (steady state) for ECL or GaAs, VHI ~ -0.8 V, VTT = -2 V, RT = 50   P = 29 mW  1/8-W resistors appropriate • Resistor composition & package options • Ideally the resistor should be purely resistive • ZR = R + jXR , XR 0 • However real resistors have reactance

  24. Termination resistor specifications • Resistor composition & package options • High-frequency circuit model for resistor Wire-wound resistors have a large inductive compontent Carbon-film or printed resistors have lower inductance Leaded resistors have lead inductance Surface-mount (leadless) resistors have much less inductance For high-frequency applications (low Tr) systemsinductance is a significant issue  Use leadless, chip resistors Added benefit, doesn’t require vias for mountingvias cost money and restrict routing areas Printed resistors Laser trimmed to obtain precise resistance values

  25. Termination resistor specifications • Resistor composition & package options • Surface-mounted chip resistors also have less inductive crosstalk than leaded parts when placed close together • Multi-resistor packs (packages containing multiple resistors, oftenin a single in-line package – SIP or dual in-line package – DIP)have unacceptable crosstalk due to proximity and due to a common current path • DO NOT USE THESE IN HIGH SPEED DESIGNS

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