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Dealing with Hazards Mite 3

Dealing with Hazards Mite 3. Ellen Spertus MCS 111 November 13, 2003. Review: Hazards. What’s a control hazard? What’s a data hazard?. Stages IF ID(RR) EX MEM WB. Sample code. sub $2 , $1, $3 and $12, $2 , $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100( $2 ).

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Dealing with Hazards Mite 3

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  1. Dealing with HazardsMite 3 Ellen Spertus MCS 111 November 13, 2003

  2. Review: Hazards • What’s a control hazard? • What’s a data hazard? Stages • IF • ID(RR) • EX • MEM • WB

  3. Sample code sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2)

  4. Interpreting the diagram • Time axis • Instruction axis • Stages • What does it mean when • a colored line goes to the right? • a colored line goes straight down? • a colored line goes to the left?

  5. How can we run sample code? • Inserting nops (“no operation”s) • sll $0, $0, 0 • Adding new datapaths to speed value to where it is needed

  6. lw $5, 3($0) sub $2,$1,$3 and $12,$2,$5 $2 $5 2 5 Figure 6.43 (p. 488)

  7. Summary: Forwarding • Hazards that forwarding can solve • Hazards that can’t be solved by forwarding

  8. Hazard requiring stalling Figure 6.44 (p. 489)

  9. What should happen on a stall? • Instructions further through the pipeline should keep going • The stalled instruction should stay at the same stage • Instructions earlier in the pipeline should

  10. From Figure 6.47 (p. 493)

  11. Dealing with hazards • Data hazards • Reordering code • Forwarding or bypassing • Stalling • Control hazards

  12. Control hazards

  13. Dealing with control hazards • Add hardware to determine earlier whether a branch is taken • Static prediction • Assume branch not taken • Assume branch taken • Dynamic prediction • Branch delay slots

  14. b = c + d; if (a == 0) ... add $s1, $s2, $s3 beq $s0, $r0, foo Branch delay slots

  15. Mite 3 • Add conditional branch • New instruction format: • LS163 functionality • reset • enable (count) • load

  16. LS163: 4-bit synchronous counter • If reset’, set outputs (Q3..Q1) to zero • If load’, set outputs to inputs (P3..P1) • If enable and Cin, increment outputs

  17. Lab 6 • Design (pages 1-3) due at beginning of class Thursday, Nov. 20. • Lab due 5 PM, Tuesday, Dec. 2.

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