Cost-Based Tradeoff Analysis of Standard Cell Designs: A Study at Carnegie Mellon University

1. Cost-Based Tradeoff Analysis of Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 {pli, pkn, maly}@ece.cmu.edu

2. Motivations • Necessity for Evaluation of Designs’ Cost Effectiveness • Tendency of Manufacturing Cost Increase • Selection of Technology Which Yields the Least Cost • Emergence of Fabless Design Houses • Choice of Manufacturing Technologies • Consideration of Manufacturing from Design Perspective • Importance of Early-Stage Predictions • Reduction of Number of Design Iterations • Facilitation of Early-Stage Decision P. Li, SLIP’2000

3. Objective • Cost Prediction for Standard Cell Designs • Quickly Predict Die Size & Interconnect Yield As a Function of Number of Metal Layers • Based On a Given Placement • Predict Die Cost Based on a Wafer Cost Model • Forecast Optimal Selection of Number of Metal Layers In Terms Of Die Cost P. Li, SLIP’2000

4. Why Number of Metal Layers Matters • Affect Die Size and Yield • An Important Cost Factor P. Li, SLIP’2000

5. Approach Given Placement Interconnect Critical Area Analysis Stochastic Pseudo-Routing (Routing Estimation) Interconnect Yield Prediction Die Height Estimation Cost Prediction Die Width Estimation Size Estimate Stable? P. Li, SLIP’2000

6. Stochastic Pseudo Routing Given Placement Stochastic Pseudo-Routing Expanded/Compacted Placement Estimated Routing Utilization Defects Wafer Cost Model Interconnect Yield Prediction P. Li, SLIP’2000

7. Layout Representation • Grid Routing Model • Horizontal Routing Layers: Metal1, Metal3, Metal5 etc. • Vertical Routing Layers: Metal2, Metal4, Metal6 etc. Grid width Cell-Row Grids Cell height defined by cell library Channel Grids Channel height to be estimated Chip width to be estimated P. Li, SLIP’2000

8. Stochastic Pseudo Routing of Two-terminal Nets N • Restrict routing estimation within the bounding box of the net. • Only consider Manhattan paths having no more than two vias. • There are totally PNUM = (M+N-2) path candidates. • Assume each path candidate has a probability of 1/PNUMof being selected. M P. Li, SLIP’2000

9. Stochastic Pseudo Routing of Two-terminal Nets p2 • From Probabilities To Routing Utilization Estimates p2 p1 p1 p2 p3 p4 p2 p3 p1 p1 p4 P. Li, SLIP’2000

10. Pin1 Pin2 P4 Pin3 Pin5 Stochastic Pseudo Routing of Multi-Terminal Nets • Extension of Pseudo Routing of Two-Terminal Nets • Find A Minimum Spanning Tree • Pseudo Route Each Edge of The MST • Consider wiring sharing among MST Edges • Assume Pseudo-Routing of MST edges are independent of each other: p1 p2 Merged Segment p3 p4 Merged Region p5 P. Li, SLIP’2000

11. Die Size Estimation Given Placement Stochastic Pseudo-Routing Expanded/Compacted Placement Estimated Routing Utilization Defects Wafer Cost Model Interconnect Yield Prediction P. Li, SLIP’2000

12. Die Height Estimation • Lower Bound of Total Channel Density • Based on horizontal routing utilization estimation. • “Switchable Routing Demand” • Analogy to switchable net segments • Assign “switchable routing demand” to proper channels to minimize total channel density. Cell Rows Channels Channel Density: 4 P. Li, SLIP’2000

13. Die Width Estimation • Expand/Compact based on difference between routing demand and capacity. • Iterate on updated cell locations. Expansion Estimated Vertical Routing Utilization Compaction P. Li, SLIP’2000

14. Interconnect Yield Prediction Given Placement Stochastic Pseudo-Routing Expanded/Compacted Placement Estimated Routing Utilization Defects Wafer Cost Model Interconnect Yield Prediction P. Li, SLIP’2000

15. Interconnect Yield Prediction • Traditional Methods • Layout Based Critical Area Extraction • Requires final layouts • Accurate but time consuming: Mapex, Dracula • High-Level Interconnect Model • Relates the yield to netlist characteristics • Our Approach • Based On Routing Utilization Estimation • Empirical Routing Heterogeneity Model • Closed-Form Critical Area Expression • Linear Time Algorithm P. Li, SLIP’2000

16. Cost Prediction Stochastic Pseudo-Routing Given Placement Expanded/Compacted Placement Estimated Routing Utilization Defects Wafer Cost Model Interconnect Yield Prediction P. Li, SLIP’2000

17. Cost Prediction • Wafer Cost Model of 0.25 m CMOS Process • Prediction of Cost As Function of Number of Metal Layers • Number of Good Dies Per Wafer: Ngood(M) = Awafer / Adie(M) ·Yield(M) • Cost of A Good Die: Cdie(M) = Cwafer(M) / Ngood(M) P. Li, SLIP’2000

18. Experimental Results • Experiment Setup • Six Standard Cell Designs • Portions of Industrial DSP circuits • Comparison With Data Based On Layouts • 2-4 metal layers • Our method : die size, routing utilization and yield • Cadence tools: layout generation, critical area extraction(Dracula) and yield calculation P. Li, SLIP’2000

19. 2 1 3 4 5 6 Experimental Results Area Cadence 2 Metal • Die Size Estimation -0.1 Estimated 3 Metal -5.5 % Error 4 Metal 6.6 5.0 3.1 -19.7 -5.5 14.0 3.7 -1.7 2.8 13.4 -0.3 3.6 3.5 -7.9 17.0 6.2 Design 2 3 4 5 6 P. Li, SLIP’2000

20. Experimental Results Estimated Routing Distribution Distribution Generated by RouteTool • Routing Utilization Distribution Heavily Routed Areas P. Li, SLIP’2000

21. 2 1 3 4 5 6 Experimental Results Cadence Estimated 3 Metal 2 Metal 4 Metal • Yield Prediction Yield Design P. Li, SLIP’2000

22. Experimental Results • Cost As a Function of Metal Layers • Optimal Number of Metal Layers Cost($) Design3 Design5 P. Li, SLIP’2000

23. Summary • Fast Routing Estimation Technique • Die Size • Routing Utilization Distribution • Interconnect Yield Prediction • Cost Prediction • Prediction of Optimal Number of Metal Layers • Directions • A Priori Wire Distribution/Placement Estimation • Standard cell design style • Realistic wiring density distribution • Consideration of Circuit Performance Issues P. Li, SLIP’2000