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Utku ÖZBEK. OUTLINE. Introduction Key Features Two 64-bit cores (Intel 64 Technology) Hyper-Threading Technology Up to 16 MB of shared L3 (on die cache) Intel Cache Safe Technology Intel Virtualization Technology Demand-Based Switching (DBS) with Enhanced Intel SpeedStep technology

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outline
OUTLINE
  • Introduction
  • Key Features
    • Two 64-bit cores (Intel 64 Technology)
    • Hyper-Threading Technology
    • Up to 16 MB of shared L3 (on die cache)
    • Intel Cache Safe Technology
    • Intel Virtualization Technology
    • Demand-Based Switching (DBS) with Enhanced Intel SpeedStep technology
    • High-speed, 3-load, front-side system bus (800 MHz)
  • Performance
  • References
introduction
Introduction
  • Released on August 29, 2006, the 7100 series, codenamed Tulsa, is an improved version of Paxville MP, built on a 65 nm process
  • Designed for high-performance multi-processor server applications
  • Up to 2 times the performance of previous-generation Dual-Core Intel® Xeon® processor 7000 series
introduction1
Introduction
  • Up to 60 percent improvement on business processing
    • enterprise resource planning (ERP)
    • supply chain management (SCM)
    • customer relationship management (CRM)
  • Up to 70 percent improvement on transaction processing
  • Over to twice the performance on e-commerce applications
  • Up to 2.8x performance per watt improvement compared to previous generation.
mechanical specifications
Mechanical Specifications
  • packaged in a Flip-Chip Micro Pin Grid Array 6 (FC-mPGA6) package
  • The package components:
  • 1. Integrated Heat Spreader (IHS)
  • 2. Processor die
  • 3. FC-mPGA6 package
  • 4. Pin-side capacitors
  • 5. Package pin
key features
Key Features
  • Two 64-bit cores (Intel 64 Technology)
  • Hyper-Threading Technology
  • up to 16 MB of shared (on die cache)
  • Intel Cache Safe Technology
  • Demand-Based Switching (DBS) with Enhanced Intel SpeedStep Technology
key features1
Key Features
  • Hyper Pipelined Technology
  • Rapid Execution Engine
  • Execution Trace Cache
  • Execute Disable Bit
  • Package Thermal Specifications
dual core 64 bit cores
Dual-Core (64-bit Cores)
  • combines two independent processors into a single package
  • In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) (chip-level multiprocessing)
  • 64-bit computing
  • Run both 32-bit and 64-bit applications
  • Supports 40-bit addressing
  • provides up to 1 Terabyte of direct memory addressability
  • data bus ECC protection
    • Single-bit error correction with double-bit error detection
hyper threading technology
Hyper-Threading Technology
  • Allows each core to function as two logical processors
  • Improves processor utilization and system responsiveness for better user experience
  • Caches, execution units, and buses are shared
  • Each logical processor has its own architectural state with its own set of general purpose registers, control registers
on die cache
On Die Cache
  • Keeps more needed data closer to the cores for access faster than off-chip memory
  • each CPU core can use the L3 cache without sending a request back to the system I/O redundantly
  • Improves performance by up 60 percent for business processing (ERP, SCM, CRM)
  • Improves 70 percent for transaction processing
  • Over twice the performance for e-commerce applications
cache safe technology
Cache Safe Technology
  • Improves processor reliability
  • Allows processor and server to continue normal operation in the event of a rare L3 cache error; automatically detects and disables cache lines
  • Helps reduce downtime and processor replacements, improving TCO (Total cost of ownership)
speedstep technology
SpeedStep Technology
  • Enhanced Intel SpeedStep Technology
    • Enhanced Intel SpeedStep Technology enables the processor to switch between frequency and voltage points, which may result in platform power savings
    • In order to support this technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled
    • enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage
    • run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system
speedstep technology1
SpeedStep Technology
  • Enhanced Intel SpeedStep Technology
    • Front side bus is not altered; only the internal core frequency is changed
    • Voltage/frequency selection is software controlled by writing to processor Model Specific Registers
      • If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency
      • If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals
hyper pipelined technology
Hyper Pipelined Technology
  • 20 stage pipeline
  • Drawback of having more stages in a pipeline is an increase in the number of stages that need to be traced back in the event that the branch predictor makes a mistake, increasing the penalty paid for a misprediction
  • To address this issue, Intel devised the Rapid Execution Engine
rapid execution engine
Rapid Execution Engine
  • ALUs in the core of the CPU actually operate at twice the core clock frequency
  • Ex: in a 3.5 GHz CPU, the ALUs will effectively be operating at 7 GHz
  • The reason behind this is to generally make up for the low Instructions Per Cycle count
  • The downside is that certain instructions are now much slower than before
  • An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU
execution trace cache
Execution Trace Cache
  • The Execution Trace Cache is a level 1 (L1) cache that stores decoded micro-operations, which removes the decoder from the main execution path, thereby increasing performance.
  • Stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU can directly access the decoded micro-ops from the trace cache, thereby saving a considerable amount of time.
execute disable bit
Execute Disable Bit
  • Any section of memory designated with this attribute means that it's only to be used for storing data
  • instructions should not reside there, and cannot be executed if they do
  • Prevent buffer over-flow
    • used to prevent certain types of malicious software from taking over computers by inserting their code into another program's data storage area and running their own code from within this section
    • When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage or worm propagation
package thermal specifications
Package Thermal Specifications
  • Processors requires a thermal solution to maintain temperatures within operating limits. Without a solution:
    • If not may result in permanent damage to the processor
    • component level thermal management
      • include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS)
    • system level thermal management
      • consist of system fans combined with ducting and venting
performance
Performance
  • Scalable performance
    • Gain up to 38 percent more ERP performance
    • Up to 70 percent more transaction performance
    • Up to double the Java server performance
    • Nearly 3 times more performance per watt than the previous generation
references
References
  • http://www.intel.com/design/Xeon/documentation.htm
  • http://www.intel.com/performance/server/xeon_mp/intthru.htm
  • http://www.intel.com/business/xeon/index.htm?iid=biztab+xeonbadge
  • http://en.wikipedia.org/wiki/Xeon#7100-series_.22Tulsa.22
  • http://www.intel.com/pressroom/archive/releases/20060828comp_b.htm
  • http://www.intel.com/business/xeon/index.htm?iid=biztab+xeonbadge