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16.317 Microprocessor Systems Design I. Instructor: Dr. Michael Geiger Summer 2012 Lecture 7 Reviewing protected mode memory accesses Virtual memory Exam 2 Preview. Lecture outline. Announcements/reminders HW 2, Lab 3 due today Exam 1 regrade requests due in writing Monday, 7/30

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16 317 microprocessor systems design i

16.317Microprocessor Systems Design I

Instructor: Dr. Michael Geiger

Summer 2012

Lecture 7

Reviewing protected mode memory accesses

Virtual memory

Exam 2 Preview

lecture outline
Lecture outline
  • Announcements/reminders
    • HW 2, Lab 3 due today
    • Exam 1 regrade requests due in writing Monday, 7/30
      • Answer to 1d should be (ii), not (iii)
    • Exam 2: Wednesday, 8/1
      • List of 80386 instructions, condition codes will be posted
    • Exam 3: moved to Monday, 8/13 (not Wed 8/15)
  • Today’s lecture
    • Review:
      • Subroutine instructions
      • Protected mode memory management
    • Protected mode practice problems
    • Virtual memory
    • Exam 2 Preview

Microprocessors I: Lecture 7

review
Review
  • Subroutines: low-level functions
    • When called, address of next instruction saved
      • Return instruction ends routine; goes to that point
    • May need to save state on stack
  • 80386 specifics
    • CALL <proc>: call procedure
      • <proc> can be label (16-/32-bit imm), reg, mem
    • RET: return from procedure
    • Saving state to stack: push instructions
      • Store data “above” current TOS; decrement SP
      • Basic PUSH stores word or double word
      • Directly storing flags: PUSHF
      • Storing all 16-/32-bit general purpose registers: PUSHA/PUSHAD
    • Restoring state: POP/POPF/POPA/POPAD

Microprocessors I: Lecture 7

review1
Review
  • Protected mode
    • Supports memory management, multitasking, protection
    • Changes in control/flag registers, IP, memory accesses
  • Selectors: pointers into descriptor tables
    • Contains requested privilege, global/local, and table index
  • Descriptors: provide info about segments
    • 8 bytes in length
    • 4 bytes: base address
    • 2 bytes: limit (max offset within segment)
      • Segment size = (limit + 1) bytes
    • 2 bytes: access info (privilege, R/W, executable, etc.)

Microprocessors I: Lecture 7

review cont
Review (cont.)
  • Descriptors stored in descriptor tables
    • Specific memory range dedicated to table
    • GDTR points to global descriptor table
      • Contains base address, limit for GDT
    • LDTR cache points to global descriptor table
      • Contains base address, limit for current LDT
      • Values loaded from entry in GDT, pointed to by LDTR
  • Global memory access
    • Selector indicates access is global (TI == 0)
    • Index field in selector chooses descriptor from GDT
    • Descriptor provides starting address of segment
  • Local memory access
    • Selector indicates access is local (TI == 1)
    • Index field in selector chooses descriptor from LDT
    • Descriptor provides starting address of segment

Microprocessors I: Lecture 7

protected mode examples
Protected mode examples
  • See problems posted on web

Microprocessors I: Lecture 7

exam 2 notes
Exam 2 notes
  • Allowed
    • One 8.5” x 11” double-sided sheet of notes
    • Calculator
  • Instruction/condition code list provided
  • No other notes or electronic devices (phone, laptop, etc.)
  • You will have 2 hours to complete exam, unless you arrive after 3:00
    • Late arrivals need legit excuse to get full 2 hours
  • Covers all lectures after Exam 1
  • Format similar to Exam 1
    • 1 multiple choice question
    • 2 short problems to solve/code sequences to evaluate

Microprocessors I: Lecture 7

review bit test scan flag control
Review: Bit test/scan, flag control
  • Bit test instructions
    • Check state of bit and store in CF
    • Basic test (BT) leaves bit unchanged
    • Can also set (BTS), clear (BTR), or complement bit (BTC)
  • Bit scan instructions
    • Find first non-zero bit and store index in dest.
    • Set ZF = 1 if source non-zero; ZF = 0 if source == 0
    • BSF: scan right to left (LSB to MSB)
    • BSR: scan left to right (MSB to LSB)
  • Flag control instructions
    • Initialize carry flag to 0 (CLC), 1 (STC), or ~CF (CMC)
    • Set (STI) or clear (CLI) interrupt flag
    • Transfer flags to (LAHF) or from (SAHF) register AH

Microprocessors I: Lecture 7

review compare set on condition
Review: Compare, set on condition
  • CMP D, S
    • Flags show result of (D) – (S)
  • Condition codes: mnemonics implying certain flag conditions
  • SETcc D
    • Sets single byte destination to all 1s (FFH) if condition true; all 0s (00H) if condition false
    • Can be used to build up complex conditions

Microprocessors I: Lecture 7

review jump instructions
Review: jump instructions
  • Two general types of jump
    • Unconditional: JMP <target>
      • Always go to target address
    • Conditional: Jcc <target>
      • Go to target address if condition true
  • Target can be:
    • Intrasegment: same segment; only IP changes
      • Add constant 8/16 bit offset, or
      • Replace IP with 16 bit value from register/memory
    • Intersegment: different segment; CS/IP both change
      • Target is 32-bit value
      • Upper 16 bits overwrite CS; lower bits overwrite IP
  • Jump applications
    • Conditional statements (if/else)
    • Loops (pre-/post-tested)

Microprocessors I: Lecture 7

review loop instructions
Review: loop instructions
  • Loop instructions
    • Combines CX decrement with JNZ test
    • May add additional required condition
      • LOOPE/LOOPZ: loop if ((CX != 0) && (ZF == 1))
      • LOOPNE/LOOPNEZ: loop if (CX != 0) && (ZF == 0))

Microprocessors I: Lecture 7

review subroutines
Review: subroutines
  • Subroutines: low-level functions
    • When called, address of next instruction saved
      • Return instruction ends routine; goes to that point
    • May need to save state on stack
  • 80386 specifics
    • CALL <proc>: call procedure
      • <proc> can be label (16-/32-bit imm), reg, mem
    • RET: return from procedure
    • Saving state to stack: push instructions
      • Store data “above” current TOS; decrement SP
      • Basic PUSH stores word or double word
      • Directly storing flags: PUSHF
      • Storing all 16-/32-bit general purpose registers: PUSHA/PUSHAD
    • Restoring state: POP/POPF/POPA/POPAD

Microprocessors I: Lecture 7

review protected mode
Review: protected mode
  • Protected mode
    • Supports memory management, multitasking, protection
    • Changes in control/flag registers, IP, memory accesses
  • Selectors: pointers into descriptor tables
    • Contains requested privilege, global/local, and table index
  • Descriptors: provide info about segments
    • 8 bytes in length
    • 4 bytes: base address
    • 2 bytes: limit (max offset within segment)
      • Segment size = (limit + 1) bytes
    • 2 bytes: access info (privilege, R/W, executable, etc.)

Microprocessors I: Lecture 7

review cont1
Review (cont.)
  • Descriptors stored in descriptor tables
    • Specific memory range dedicated to table
    • GDTR points to global descriptor table
      • Contains base address, limit for GDT
    • LDTR cache points to global descriptor table
      • Contains base address, limit for current LDT
      • Values loaded from entry in GDT, pointed to by LDTR
  • Global memory access
    • Selector indicates access is global (TI == 0)
    • Index field in selector chooses descriptor from GDT
    • Descriptor provides starting address of segment
  • Local memory access
    • Selector indicates access is local (TI == 1)
    • Index field in selector chooses descriptor from LDT
    • Descriptor provides starting address of segment

Microprocessors I: Lecture 7

final notes
Final notes
  • Next time: Exam 2
  • Reminders
    • HW 2, Lab 3 both due today
    • Lecture Friday: PIC intro
    • HW 3 to be posted today, due 8/6
    • Lab 4 coming soon, due 8/8
      • Note: lab uses PIC microcontroller—will have to check out kit from lab, so you’ll need to contact me to do so

Microprocessors I: Lecture 7