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Digital Systems

14. Digital Systems. S. Q. Inputs. Outputs. R. Q. S. Q. R. 0. 0. Present state. 0. 1. Reset. 1. 0. Set. 1. 0. Disallowed. Figure 14.1 RS flip-flop symbol and truth table. S. R. Q. Time. 1. 0. 1. 1. S. 0. 0. 1. 0. 0. 0. 1. 1. R. 0. 1. 0. 0. 0. 0. 0.

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Digital Systems

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  1. 14 Digital Systems

  2. S Q Inputs Outputs R Q S Q R 0 0 Present state 0 1 Reset 1 0 Set 1 0 Disallowed Figure 14.1 RS flip-flop symbol and truth table

  3. S R Q Time 1 0 1 1 S 0 0 1 0 0 0 1 1 R 0 1 0 0 0 0 0 1 Q 0 0 0 0 0 1 0 0 0 0 Flip-flop Flip-flop Flip-flop Flip-flop is reset is reset is set is set 1 0 1 (but Q = 0) 0 0 1 already Figure 14.2 Timing diagram for the RS flip-flop

  4. S S Q Q Q Q R R Figure 14.3 Logic gate implementation of the RS flip-flop

  5. Preset Preset ( P ) Clear S Q S E R Q Q R Enable Clear ( C ) Timing diagram Figure 14.4 RS flip-flop with enable, present, and clear lines

  6. Q D D S Q Enable E Q E R Q D Enable Q Figure 14.5 Data latch and associated timing diagram

  7. D Q 1 D Q Q S Q D Q S 2 2 1 1 R Q Q Q R Q = Q 1 2 1 2 2 Q CLK E E 1 2 CLK CLK Device symbol Functional diagram Timing diagram Figure 14.6 D flip-flop functional diagram, symbol, and timing waveforms

  8. Master Slave Q Q Q J Q S S 1 2 2 1 J CLK CLK E E Q Q 1 2 2 K Q R K Q R 1 1 2 Device symbol Functional diagram Figure 14.7 JK flip-flop functional diagram and device symbol

  9. J Q CLK K Q JK flip-flop Q J K n n n +1 0 0 Q n 0 1 0 (reset) 1 0 1 (set) Q (toggle) 1 1 n Figure 14.8 Truth table for JK flip-flop

  10. State Reset Input pulses b b b 2 1 0 0 0 0 0 1 0 0 1 counter binary 3-bit Clock 2 0 1 0 input 3 0 1 1 4 1 0 0 5 1 0 1 b b b 1 2 0 6 1 1 0 Functional representation of binary counter 7 1 1 1 Timing table Clock t b 0 t b 1 t b 2 t Timing diagram Figure 14.10 Binary up counter functional representation, state table, and timing waveforms

  11. Input pulses b b b b 3 2 1 0 0 0 0 0 0 Reset 1 0 0 0 1 2 0 0 1 0 4-bit 3 0 0 1 1 Clock binary counter 4 0 1 0 0 5 0 1 0 1 b b b b 3 2 1 0 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 Reset Figure 14.11 Decade counter

  12. Q Q Q Input 3 2 1 1 1 1 0 0 0 0 0 1 0 1 0 J J Q Q Q J 0 1 1 Clock CLK CLK CLK input 1 0 0 K K K 1 0 1 1 1 0 Q Q Q 3 2 1 Figure 14.12 Ripple counter 1 1 1

  13. Q Q Q 0 1 2 Q Q Q 1 T T T 0 1 2 CLK CLK CLK Q Q Q 0 2 1 Clock input Figure 14.15 Three-bit synchronous counter

  14. Init Q Q Q Q 3 2 1 0 PR CLR CLR CLR S Q Q Q Q S S S 3 2 1 0 CLK CLK CLK CLK Q R R Q R Q R Q 3 2 1 0 Clock Figure 14.16 Ring counter input

  15. Q Q Q Q 0 1 2 3 Q Q Q D D D D Q 0 2 3 1 CLK CLK CLK CLK “Load” input b b b b 0 1 2 3 Figure 14.21 Four-bit parallel register

  16. Q Q Q Q 0 1 2 3 b Serial 1 Serial Q Q D Q D D D Q 1 input output 2 3 0 CLK CLK CLK CLK Clock input Figure 14.22 Four-bit shift register

  17. D a C b B c A BCD to d seven-segment e decoder f g Figure 14.24

  18. 1 Q Q Q T T T 3 2 1 3 2 1 Q Q Q 3 2 1 CLK 000 001 010 011 111 110 101 100 Figure 14.26 Three-bit binary counter and state diagram

  19. 01 00 10 11 Figure 14.27 State diagram of a modulo-4 up-down counter

  20. Q Q Q Q 1 2 1 2 x x 1 0 d 0 0 d 0 1 0 1 0 d d 0 1 0 S R 1 1 Q Q Q Q 1 2 1 2 x x 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 S R 2 2 Figure 14.28 Karnaugh maps for flip-flop inputs in modulo-4 counter

  21. x Q S 1 1 R Q 1 1 Q S 2 2 Q R 2 2 Figure 14.29 Implementation of modulo-4 counter

  22. Sensor signals Other computers and instrumentation systems Signal interface Communication Software Microcomputer User links Signal interface To To displays actuators Figure 14.30 Structure of a digital data acquisition and control system

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