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PIC 16F877. Architectural Features :-. Harvard Architecture Reduced Instruction Set Long word Instructions Single Word Instructions Single Cycle Instructions Instruction Pipelining Register File structure Orthogonal (Symmetric) Instruction. Von Neumann. Harvard Architecture.

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architectural features

Architectural Features :-

Harvard Architecture

Reduced Instruction Set

Long word Instructions

Single Word Instructions

Single Cycle Instructions

Instruction Pipelining

Register File structure

Orthogonal (Symmetric) Instruction

harvard architecture

Von Neumann

Harvard Architecture
  • Common Program & Data Memories
  • Single Bus for both program & Data
  • Reduced Bandwidth
  • Multiple access through single Bus
  • Separate Program & Data Memories
  • Separate Buses
  • Improves Bandwidth
  • Single access through wider Program Bus & Program memory
long word instructions
Long Word Instructions:
  • Long word instructions have a wider Instruction bus Width of bus indicates the width of memory. In case of Von neumann, instruction can be of 8 bits only. In case of Harvard, instruction can be of upto 14 bits. Here, Program memory width is optimized to meet architectural requirements.
single word instruction
Single Word Instruction:
  • Harvard Architecture: Opcodes are 14 Bit wide  Single word instructions are possible. Fetches the whole word in single cycle b’coz width of IB is 14 bit. No. of program memory locations = No. of Instructions.Von – Neumann: Opcodes are 8 Bit wide  Single word instructions is not possible. Multiple Access is required to fetch 14 – bit wide instructions. No. of Instructions that can be stored = No. of Program Memory locations / 2
instruction pipelining
Instruction Pipelining:
  • Harvard Architecture: 2 stage Pipeline : Fetch & Execute. For Fetch  1 instruction cycle = Tcy For Execute  1 instruction cycle = Tcy Due to overlap, of fetch2 of current instruction and Execute1 of the previous instruction, instruction execution time = TcyVon – Neumann: No Pipelining No Overlapping  Instruction execution time = 2 * Tcy.
single cycle instruction
Single Cycle Instruction:
  • Harvard Architecture: As program memory bus is 14 bit wide, whole instruction can be executed in single cycle. There may be a delay of 1 instruction cycle ( Tcy), if result of the instruction is modified.Von – Neumann: Multicycle Instruction.
reduced instruction set
Reduced Instruction Set:
  • Harvard Architecture: Instructions are well designed and orthogonal (Symmetric). So , fewer instructions are required to perform the needed task.Von – Neumann: More no. of Instructions  CISC.
register file architecture
Register File Architecture:
  • Harvard Architecture: Registers are part of data memory that can be accessed directly or indirectlyVon – Neumann: More no. of Instructions  CISC.
orthogonal instructions
Orthogonal Instructions:
  • Harvard Architecture: Orthogonal instructions makes it possible to carry out any operation on any register using any addressing mode. “Special Instructions”  makes programming more simple. Mid range instructions : SLEEP : Places the device in lower power mode. CLRWDT : Verifies the chip is operating properly or not by preventing the on chip Watch Dog Timer (WDT) from overflowing and resetting the device.

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(8k x 14bit)



(8 x 14bit)



(512 x 8bit)

central processing unit
Central Processing Unit:
  • CPU is the brain of the processor. It performs the fetching of the instructions from program memory, decoding of the instruction and execution of the instructions. CPU uses the instructions stored in program memory. Some of the instructions needs data. To make the operations on the data, ALU is required. In addition to the Arithmatic and logical operations, ALU controls the status bits in STATUS Registers.