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CHAPTER 2 COMPUTER EVOLUTION. CSNB123 coMPUTER oRGANIZATION. Evolution. First Generation. Second Generation. ENIAC. E lectronic N umerical I ntegrator A nd C omputer Eckert and Mauchly University of Pennsylvania Trajectory tables for weapons Started 1943 Finished 1946

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Chapter 2 computer evolution

CHAPTER 2COMPUTER EVOLUTION

CSNB123 coMPUTERoRGANIZATION

Systems and Networking


Evolution
Evolution

First Generation

Second Generation

Systems and Networking



Eniac
ENIAC

  • Electronic Numerical Integrator And Computer

  • Eckert and Mauchly

  • University of Pennsylvania

  • Trajectory tables for weapons

  • Started 1943

  • Finished 1946

    • Too late for war effort

  • Used until 1955

Systems and Networking


Eniac 2
ENIAC (2)

  • Decimal (not binary)

  • 20 accumulators of 10 digits

  • Programmed manually by switches

  • 18,000 vacuum tubes

  • 30 tons

  • 15,000 square feet

  • 140 kW power consumption

  • 5,000 additions per second

Systems and Networking



Von neumann turing machine
Von Neumann / Turing Machine

  • Stored Program concept

    • Main memory storing programs and data

    • ALU operating on binary data

    • Control unit interpreting instructions from memory and executing

  • Input and output equipment operated by control unit

Systems and Networking


Von neumann turing machine example
Von Neumann / Turing Machine - Example

http://www.arcadefire.com/wp/wp-content/uploads/2010/10/turing11.jpg

Systems and Networking


Von neumann machine structure
Von Neumann Machine - Structure

Main Memory (M)

Central Processing Unit (CPU)

I/O Equipment (I,O)

Arithmetic Logic Unit (CA)

Program Control Unit (CC)

Systems and Networking


Von neumann turing machine 2
Von Neumann / Turing Machine (2)

  • Princeton Institute for Advanced Studies

    • IAS

  • Completed 1952

Systems and Networking


IAS

  • 1000 x 40 bit words

    • Binary number

    • 2 x 20 bit instructions

  • Set of registers (storage in CPU)

    • Memory Buffer Register

    • Memory Address Register

    • Instruction Register

    • Instruction Buffer Register

    • Program Counter

    • Accumulator

    • Multiplier Quotient

Systems and Networking


Ias structure
IAS – Structure

Arithmetic-logic Unit (ALU)

I/O Equipment (I,O)

AC

MQ

Arithmetic-logic Circuits

MBR

Program Control Unit

IBR

PC

Main Memory (M)

IR

MAR

Control Signals

Control Circuits

Systems and Networking


Ias computer example
IAS Computer - Example

http://www.comsci.us/history/images/ias.jpg

Systems and Networking




Univac example
UNIVAC - Example

http://archive.computerhistory.org/resources/still-image/UNIVAC/Univac_1.charles_collingwood.1952.102645279.lg.jpg

Systems and Networking



IBM

Systems and Networking


Ibm 701
IBM 701

http://www-03.ibm.com/ibm/history/exhibits/701/images/141511_Large.jpg

Systems and Networking


Ibm 702
IBM 702

http://www.ed-thelen.org/comp-hist/BRL61-0396.jpg

Systems and Networking


Ibm 700 7000
IBM 700/7000

https://upload.wikimedia.org/wikipedia/commons/thumb/b/b9/NASAComputerRoom7090.NARA.jpg/280px-NASAComputerRoom7090.NARA.jpg

Systems and Networking


Second generation machine
Second Generation Machine

Systems and Networking


Transistors
Transistors

  • Made from Silicon (Sand)

  • Invented 1947 at Bell Labs

  • William Shockley et al.

  • Replaced vacuum tubes

  • Solid State device

Systems and Networking


Advantages of transistors
Advantages of Transistors

  • Smaller

  • Cheaper

  • Less heat dissipation

Systems and Networking


Transistors based computers
Transistors Based Computers

  • Second generation machines

  • NCR & RCA produced small transistor machines

  • IBM 7000

  • DEC - 1957

    • Produced PDP-1

Systems and Networking


Microelectronics
Microelectronics

  • Literally - “small electronics”

  • A computer is made up of gates, memory cells and interconnections

  • These can be manufactured on a semiconductor

Systems and Networking


Overall generations of computer
Overall Generations of Computer

Systems and Networking


Moore s law
Moore’s Law

Number of transistors on a chip will double every year

Systems and Networking


Moore s law 2
Moore’s Law (2)

  • Gordon Moore – co-founder of Intel

  • Increased density of components on chip

  • Since 1970’s development has slowed a little

    • Number of transistors doubles every 18 months

Systems and Networking


Moore s law 3
Moore’s Law (3)

  • Cost of a chip has remained almost unchanged

  • Higher packing density means shorter electrical paths, giving higher performance

  • Smaller size gives increased flexibility

  • Reduced power and cooling requirements

  • Fewer interconnections increases reliability

Systems and Networking


Growth in cpu transistor count
Growth in CPU Transistor Count

Systems and Networking


Ibm 360 series
IBM 360 series

  • 1964

  • Replaced (& not compatible with) 7000 series

  • First planned “family” of computers

    • Similar or identical instruction sets

    • Similar or identical O/S

    • Increasing speed

    • Increasing number of I/O ports (i.e. more terminals)

    • Increased memory size

    • Increased cost

  • Multiplexed switch structure

Systems and Networking


Dec pdp 8
DEC PDP-8

  • 1964

  • First minicomputer (after miniskirt!)

  • Did not need air conditioned room

  • Small enough to sit on a lab bench

  • $16,000

    • $100k+ for IBM 360

  • Embedded applications & OEM

  • Bus Structure

Systems and Networking


Dec pdp 8 bus structure
DEC PDP-8 – Bus Structure

Systems and Networking


Semiconductor memory
Semiconductor Memory

  • 1970

  • Fairchild

  • Size of a single core

    • i.e. 1 bit of magnetic core storage

  • Holds 256 bits

  • Non-destructive read

  • Much faster than core

  • Capacity approximately doubles each year

Systems and Networking


Intel
Intel

Systems and Networking


Speed up
Speed Up

  • Pipelining

  • On board cache

  • On board L1 & L2 cache

  • Branch prediction

  • Data flow analysis

  • Speculative execution

Systems and Networking


Performance balance
Performance Balance

  • Processor speed increased

  • Memory capacity increased

  • Memory speed lags behind processor speed

Systems and Networking


Logic and memory performance gap
Logic and Memory Performance Gap

Systems and Networking


Logic and memory performance gap solutions
Logic and Memory Performance Gap - Solutions

  • Increase number of bits retrieved at one time

    • Make DRAM “wider” rather than “deeper”

  • Change DRAM interface

    • Cache

  • Reduce frequency of memory access

    • More complex cache and cache on chip

  • Increase interconnection bandwidth

    • High speed buses

    • Hierarchy of buses

Systems and Networking


I o devices
I/O Devices

  • Peripherals with intensive I/O demands

  • Large data throughput demands

  • Processors can handle this

  • Problem moving data

Systems and Networking


I o devices solutions
I/O Devices - Solutions

  • Caching

  • Buffering

  • Higher-speed interconnection buses

  • More elaborate bus structures

  • Multiple-processor configurations

Systems and Networking


Typical i o device data rates
Typical I/O Device Data Rates

Systems and Networking


Key is balance
Key is Balance

  • Processor components

  • Main memory

  • I/O devices

  • Interconnection structures

Systems and Networking


Improvements in chip organization and architecture
Improvements in Chip Organization and Architecture

  • Increase hardware speed of processor

    • Fundamentally due to shrinking logic gate size

      • More gates, packed more tightly, increasing clock rate

      • Propagation time for signals reduced

  • Increase size and speed of caches

    • Dedicating part of processor chip

      • Cache access times drop significantly

Systems and Networking


Improvements in chip organization and architecture 2
Improvements in Chip Organization and Architecture (2)

  • Change processor organization and architecture

    • Increase effective speed of execution

    • Parallelism

Systems and Networking


Problems with clock speed and login density
Problems with Clock Speed and Login Density

  • Power

    • Power density increases with density of logic and clock speed

    • Dissipating heat

  • RC delay

    • Speed at which electrons flow limited by resistance and capacitance of metal wires connecting them

    • Delay increases as RC product increases

    • Wire interconnects thinner, increasing resistance

    • Wires closer together, increasing capacitance

  • Memory latency

    • Memory speeds lag processor speeds

Systems and Networking


Problems with clock speed and login density solution
Problems with Clock Speed and Login Density - Solution

  • More emphasis on organizational and architectural approaches

Systems and Networking


Intel microprocessor performance
Intel Microprocessor Performance

Systems and Networking


Increased cache capacity
Increased Cache Capacity

  • Typically two or three levels of cache between processor and main memory

  • Chip density increased

    • More cache memory on chip

      • Faster cache access

  • Pentium chip devoted about 10% of chip area to cache

  • Pentium 4 devotes about 50%

Systems and Networking


More complex execution logic
More Complex Execution Logic

  • Enable parallel execution of instructions

  • Pipeline works like assembly line

    • Different stages of execution of different instructions at same time along pipeline

  • Superscalar allows multiple pipelines within single processor

    • Instructions that do not depend on one another can be executed in parallel

Systems and Networking


Diminishing returns
Diminishing Returns

  • Internal organization of processors complex

    • Can get a great deal of parallelism

    • Further significant increases likely to be relatively modest

  • Benefits from cache are reaching limit

  • Increasing clock rate runs into power dissipation problem

    • Some fundamental physical limits are being reached

Systems and Networking


New approach multiple cores
New Approach – Multiple Cores

  • Multiple processors on single chip

    • Large shared cache

  • Within a processor, increase in performance proportional to square root of increase in complexity

Systems and Networking


New approach multiple cores 2
New Approach – Multiple Cores (2)

  • If software can use multiple processors, doubling number of processors almost doubles performance

  • So, use two simpler processors on the chip rather than one more complex processor

Systems and Networking


New approach multiple cores 3
New Approach – Multiple Cores (3)

  • With two processors, larger caches are justified

    • Power consumption of memory logic less than processing logic

Systems and Networking


X86 evolution
x86 Evolution

  • x86 architecture dominant outside embedded systems

  • Organization and technology changed dramatically

  • Instruction set architecture evolved with backwards compatibility

  • ~1 instruction per month added

  • 500 instructions available

  • See Intel web pages for detailed information on processors

Systems and Networking


X86 evolution 2
x86 Evolution (2)

Systems and Networking


X86 8080
x86 - 8080

http://www.antiquetech.com/pictures%20full-size/C8080A.jpg

Systems and Networking


X86 evolution 3
x86 Evolution (3)

Systems and Networking


X86 pentium
x86 - Pentium

http://www.notebookcheck.net/uploads/tx_nbc2/intel_pentium_e5700_03.jpg

Systems and Networking


X86 evolution 4
x86 Evolution (4)

Systems and Networking


X86 core 2
x86 – Core 2

http://www.starbaseonline.com/hardware/Core2Duo.jpg

Systems and Networking


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