數位系統設計 901-43500

1. 數位系統設計901-43500 臺大電機系/電子所 吳安宇教授 代課：趙之昊<chihhao@access.ee.ntu.edu.tw> Slide modified from Prof. Wu’s DSD Lecture Note in 2010 Spring 2011/2/23

2. http://access.ee.ntu.edu.tw/=> course => Digital System Design 課程網頁

3. Objective • Digital system design plays an important role in implementing digital functions in modern system-on-chip (SOC) design. • In this course, we will focus on developing the design skills for undergraduate students so that they can be familiar with state-of-the-art digital front-end design skills and flow. An-Yeu Wu

4. Course Content (I) • Firstly, we will introduce the Hardware Description Language (HDL) and general front-end cell-based design flow. The chosen HDL is Verilog. We will formally cover: • HDL language syntax (basics) • Semantics and coding guideline (how to write elegant codes) • Coding for synthesis (how to write synthesizable codes; hardware design concept) • Reuse manual methodology (RMM) – How to create “reusable” codes for IP (Intellectual property) reuse • Front-end cell-based synthesis flow (how to use to state-of-the-art synthesis tools) An-Yeu Wu

5. Course Content (II) • Secondly, we will ask students to design and implement an advanced MIPS CPU. It is based on the knowledge of “Computer Architecture.” The assignment covers: • RT-level design of major blocks such as arithmetic logic unit (ALU), control unit, register file, cache unit, etc. • HDL coding, simulation, synthesis • Integration of whole design and enabling the execution of MIPS R32 binary codes • Instruction set architecture (ISA) development and extension • Enhanced RISC-based CPU design with Pipelining, Forwarding, and Hazard Control An-Yeu Wu

6. Homework • Five homework • Practice of Structural Verilog Coding • Practice of Behavior-Level Verilog Coding • Design of a Single Cycle MIPS Processor • Design of a Cache Unit • Topic Selected from Cell-Based IC Design Contest Individual Homework Team Homework An-Yeu Wu

7. Final Project • Design of a Pipelined MIPS Processor with Cache Unit: • Baseline • Implement specified instruction set (30~40 instructions) • Combine the components built in hw1~hw4 • Solvedata/control/branch hazards • Execute given binary codes and output correct results • Extension • Implement MUL/DIV/MAC instructions • Pipeline ALU and handle hazards from ALU pipelining • Other selected topics An-Yeu Wu

8. Course Schedule(1) An-Yeu Wu An-Yeu Wu pp. 8

9. Course Schedule (2) An-Yeu Wu An-Yeu Wu pp. 9

10. Textbooks • (Main Verilog coding textbook)“Verilog HDL: Digital design and modeling,” Joseph Cavanagh, CRC Press, 2007. • (Reference CPU textbook) “Computer organization and design: The hardware/software interface,” David A. Patterson and John L. Hennessy, 2008, 4th Edition. • (Reference Verilog coding textbook ) “Digital system designs and practices: Using Verilog HDL and FPGAs," Ming-Bo Lin, Wiley, 2008. An-Yeu Wu

11. Course Grading • Homework: 30% • Midterm Exam: 30% • Final Project: 35% • Impression: 5% (Attendance & Attitude). • Previous results: An-Yeu Wu

12. Suggested Background • Programming Language: Required • Logic Design :Required • Computer Organization and Design:Suggested • VLSI Design and VLSI/EDA tools: Optional An-Yeu Wu

13. Limitation • Limit • 39 students, 13 teams • 3 students as a team for hw5 and project • Priority: • EE3 • EE4 • EE2 • EE1 • Other departments • Graduate students. An-Yeu Wu

14. Major Related Courses Computer Architecture http://access.ee.ntu.edu.tw/course/CA_992/ Cover domain knowledge of computer organization and the relationship between hardware and software Textbook: David A. Patterson, and John L. Hennessy, “Computer Organization and Design – The Hardware/Software Interface”, 4th Edition, Morgan Kaufman Publishers, Inc., 2009. Digital Circuit Design Lab Project oriented practice of design and implementation of real systems FPGA-based design flow Computer-aided VLSI System Design (CVSD) – graduate course of NTUGIEE Cover more topics and back-end flow of cell-based ICdesign An-Yeu Wu

15. High-performance Digital Design in SoC Era

16. IC Design and Implementation Idea Design An-Yeu Wu

17. Digital IC Design Flow • Concept/Application • Function/Spec. definition • Algorithm exploration • Architecture design • Divide-and-conquer • Sub-module design • Design verification • System prototyping (need training!!) • RTL design • Verilog Coding/Schematic Design • Cell-based IC design flow / FPGA design flow An-Yeu Wu

18. System Specification Partition IO Spec. IO Timing Spec. An-Yeu Wu

19. Algorithm Mapping and Architecture Design System/Algorithm Level RTL Level Descriptionof hardware An-Yeu Wu

20. Design Capture Functional HDL Pre-Layout Simulation Structural Logic Synthesis Floorplanning Post-Layout Simulation Placement Physical Circuit Extraction Routing Tape-out Cell-Based IC Design Flow Front-End Design Iteration Back-End An-Yeu Wu

21. Brief Overview of Digital System Design An-Yeu Wu

22. The First Computer The Babbage Difference Engine (1832) 25,000 parts Cost: 17,470 Pounds in Year 1832 Mechanical, using gears, decimal notation An-Yeu Wu

23. ENIAC -The first electronic computer (1946) Use Vacuum Tubes as Switching Components (Binary) An-Yeu Wu

24. Now: Computer Everywhere Advances of VLSI Technology Brings Computer Everywhere An-Yeu Wu

25. Technologies for building processors and memories • Vacuum tube • An electronic component, predecessor of the transistor, that consists of a hollow glass tube about 5 to 10 cm long from which as much air has been removed as possible and which uses an electron beam to transfer data • Transistor • An ON/OFF switch controlled by an electric signal • Very large scale integrated (VLSI) circuit • A device containing hundreds of thousands to millions of transistors An-Yeu Wu

26. Vacuum Tube An-Yeu Wu

27. The Transistor Revolution First transistor Bell Labs, 1948 An-Yeu Wu

28. Discrete Transistors An-Yeu Wu

29. The MOS Transistor Polysilicon Aluminum/Cu Channel length: The distance between Source and Drain 0.18um/0.13um: this year 90nm: next year An-Yeu Wu

30. The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 An-Yeu Wu

31. Gate and Circuit Level Design An-Yeu Wu

32. Mapping of Layout to IC Layers An-Yeu Wu

33. Layout of an CMOS Inverter An-Yeu Wu

34. Physical Design An-Yeu Wu

35. Physical Layout of your design An-Yeu Wu

36. The “Timing Closure” Problem Iterative Removal of Timing Violations (white lines) Courtesy Synopsys An-Yeu Wu

37. The chip manufacturing process An-Yeu Wu

38. Humorous Analogy betweenChip Fabricating Process and Pizza Making An-Yeu Wu

39. Moore’s Law • In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. • He made a prediction that semiconductor technology will double its effectiveness every 18~24 months Electronics, April 19, 1965. An-Yeu Wu

40. Moore’s Law: Driving Technology Advances • Logic capacity doubles per IC at regular intervals (1965). • Logic capacity doubles per IC every 18 months (1975). An-Yeu Wu

41. Technologies for building processors and memories Relative performance per unit cost of technologies used in computers over time An-Yeu Wu

42. Engineering Productivity Gap Engineering productivity has not been keeping up with silicon gate capacity for several years. Companies have been using larger design teams, making engineers work longer hours, etc., but clearly the limit is being reached. An-Yeu Wu

43. Why must HDL tools & IP Reuse? Design productivity crisis: Divergence of potential design complexity and designer productivity An-Yeu Wu

44. SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+ Design Abstraction Levels An-Yeu Wu

45. HDL and Moore’s Law • HDL – Hardware Description Language • Why use an HDL ? • Hardware is becoming very difficult (and too big!) to design directly • HDL is easier and cheaper to explore different design options • Reduce time and cost to verify your digital designs in VLSI implementations An-Yeu Wu

46. Verilog HDL • Feature • HDL has high-level programming language constructs and constructs to describe the connectivity of your circuit. • Ability to mix different levels of abstraction freely • One language for all aspects of design, test, and verification • Functionality as well as timing • Concurrently simulate behaviors of multiple hardware blocks in simulator • Support timing simulation for your design An-Yeu Wu

47. Level of Abstraction for Design and Verification System concept Algorithm Increasing detailed realization & complexity Architecture Increasing behavioral abstraction Register Transfer Level Gate Level Transistor Level W1: DSD Course Overview 2009.2.18 An-Yeu Wu An-Yeu Wu pp. 47

48. Design Model Domain Behavioral level of abstraction Abstract Structural Physical Architecture System Synthesis Architecture RTL level Design Synthesis Algorithm Structural Logic level Design Synthesis RTL Verification Logic Design Gate Verification Layout Design Switch Verification Verilog HDL in Different Level An-Yeu Wu

49. Cell-based IC Design Flow Back-End Design Specification Pre-Synthesis Sign-Off Cell Placement, Scan Chain & Clock Tree Insertion, Cell Routing Design Partition Synthesize and MapGate-Level Netlist Verify Physical & Electrical Design Rules Design Entry-Verilog Behavioral Modeling Post-Synthesis Design Validation Extract Parasitics Simulation/Functional Verification Post-SynthesisTiming Verification Post-LayoutTiming Verification Design Integration & Verification Test Generation &Fault Simulation Design Sign-Off Production-ReadyMasks Front-End Designs An-Yeu Wu