1 / 86

Globally Asynchronous Locally Synchronous (GALS) Systems

Globally Asynchronous Locally Synchronous (GALS) Systems. Asynchronous Circuits Design Course 86-87-2. Agenda. Motivation Asynchronous Design GALS Definition GALS Advantages GALS Problem Coping With Metastability SoC Communication Infrastructure Architectures GALS Design Style Taxonomy

drucilla
Download Presentation

Globally Asynchronous Locally Synchronous (GALS) Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Globally Asynchronous Locally Synchronous (GALS) Systems Asynchronous Circuits Design Course 86-87-2

  2. Agenda • Motivation • Asynchronous Design • GALS Definition • GALS Advantages • GALS Problem • Coping With Metastability • SoC Communication Infrastructure Architectures • GALS Design Style Taxonomy • Pausible Clock GALS Design Style • Asynchronous Interface GALS Design Style • Loosely synchronous GALS design style • GALS SoC Communication Infrastructure Architectures • Designed and Fabricated GALS Systems and Chips

  3. Motivation • SoC design methodology • “Divide” complex chips into several independent functional blocks And • “Conquer” each of them using standard synchronous methodologies and existing CAD tools. • An on-chip infrastructure connects them to form a functional system. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  4. Motivation (Cont’d) • Dividing a chip into smaller blocks, Keeps technology scaling problems, such as clock skew, manageable. • Only for individual blocks, • Not for the interconnects. • Connecting the elements by relatively long wires, • Don’t scaled well in deep sub micron technologies. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  5. Motivation (Cont’d) • Major problems in having various synchronous on-chip communications • Modularity and Design Reuse • Electromagnetic Interference (EMI) • Worst Case Performance • Clock Power Consumption • Clock Skew M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  6. Asynchronous Design • Smoother handling of both fabrication time and run-time variability • Delay matching, completion detection • Eliminating clock power consumption, clock skew, and EMI • Modular design • Timing assumptions are explicit in the handshaking protocols • The circuit works faster • Exploiting average case rather than worst case performance M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  7. Asynchronous Design (Cont’d) • Asynchronous design is a more difficult task compares to synchronous design • Glitch-free circuits have to be generated. • Absence of industrial tool support • Lack of a mature tool flow. • High overhead in terms of area, delay, and possibly even power consumption • Dual rail data path, and collecting Ack signals from every gate output M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  8. GALS Definition • Globally Asynchronous Locally Synchronous system design • Aims at filling the gap between the purely synchronous and asynchronous domains. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  9. GALS Definition (Cont’d) • Consists of synchronous modules on a chip communication asynchronously. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005 T. Meincke, et al., “Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI Architecture”

  10. GALS Definition (Cont’d) • Although most digital circuits remain synchronous, many designs feature multiple clock domains, often running at different frequencies. • Using an asynchronous interconnect decouples the timing issues for the separate blocks. • Systems employing such schemes are called Globally Asynchronous, Locally Synchronous (GALS). Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”

  11. GALS Definition (Cont’d) The first use of the term GALS was by Chapiro in his 1984 doctoral dissertation.

  12. GALS Definition (Cont’d) • Each Synchronous module: • SB (Synchronous Block) • SI (Synchronous Island) • IP Block (Intellectual Property Block) • PU (Processing Unit) • Functional Block (FB) • …

  13. GALS Definition (Cont’d) • GALS systems have diverse definitions, titles, and antitypes • Multiple asynchronous clock domains • Special data, control, and verification handling C. E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs”, 2001 • Clock domain crossing issues CLOCK DOMAIN CROSSING, CLOSING THE LOOP ON CLOCK DOMAIN FUNCTIONAL IMPLEMENTATION PROBLEMS, TECHNICAL PAPER, Cadence • Cross domain communication Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007 • System timing Issues Robert Mullins, http://www.cl.cam.ac.uk/users/rdm34 • Delay-insensitive communication • Skew-insensitive communication • ...

  14. GALS Definition (Cont’d) • The most rigorous definition: • Only the systems with blocks, clocked Independently from local clock generators, interconnected asynchronously. R. Mullins, and S. Moore, “Demystifying Data-Driven and Pausible Clocking Schemes”, 2007 • The most universal definition: • A system that it’s global clock network is removed! • Not a single-clocked digital system! Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007 • Not a pure, one-clock synchronous system! C. E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs”, 2001

  15. GALS Definition (Cont’d) Synchronous to Delay-Insensitive Approaches to System Timing Timing Assumptions Isochronic Forks Wire Delay Local Relative Sub-System Local Global None Synchronous Delay Insensitive Quasi-Delay Insensitive Bundled Data Pausible clocks and locally triggered clock pulses Multiple clocks Less Detection Local Clocks/ Interaction with data (becoming aperiodic) Robert Mullins Presentation, “Asynchronous vs. Synchronous Design Techniques for NoCs“, “The Status of the Network-on-Chip Revolution: Design Methods, Architectures and Silicon Implementation”, (Tutorial) International Symposium on System-on-Chip, Tampere, Finland. November 14th, 2005.

  16. GALS Advantages • Increased ease of functional-block reuse • Can facilitate fast block reuse by providing wrapper circuits to handle interblock communication across clock domain boundaries. • Simplified timing closure • Power advantages due to heterogeneous clocking • By clocking different blocks at their minimum speeds. • By allowing fine tuning of the supply voltages and clock speeds for different functional blocks • By dynamic voltage and frequency scaling • By eliminating the need for a global, low-skew clock. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  17. GALS Advantages (Cont’d) • Allow synchronous design of components at their own optimum clock frequency • But facilitates asynchronous communication between modules • Leads to design flow fairly similar to the synchronous flow • But with a few additional components which enable asynchronous communication. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  18. GALS Advantages (Cont’d) • Eliminates the global clock leading to huge reduction of power consumption and alleviating the clock skew problem. • Facilities modular system design which is scalable. • Because of close resemblance to synchronous design, can attract the attention of synchronous designers who are not willing to experiment with asynchronous design. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  19. GALS Problem • GALS: communication framework in which local clocks are either unsynchronized or paused • There is a risk of metastability at the interfaces which is not present in traditional speed independent or delay insensitive asynchronous circuits. Metastability in Data Synchronizing and Communicating M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  20. GALS Problem (Cont’d) • Metastability • is a condition where the voltage level of a signal is • at an intermediate level — neither 0 or 1 — • and which may persist for an indeterminate amount of time. M. Amde et al., “Asynchronous On-Chip Networks”, IEE 2005

  21. Coping With Metastability • Timing-Safe Methods • Allocate a fixed period of time for metastability to resolve, e.g. two flip-flop synchronizer • Please refer to C. E. Cummings, “Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs”, 2001 “CLOCK DOMAIN CROSSING, CLOSING THE LOOP ON CLOCK DOMAIN FUNCTIONAL IMPLEMENTATION PROBLEMS”, TECHNICAL PAPER, Cadence • Value-Safe Methods • Wait for metastability to resolve, e.g. clock stretching or pausing techniques • Clock is generated locally • Value-safe ideas are less well understood, avoided by industry Robert Mullins Presentation, “Demystifying Data-Driven and Pausible Clocking Schemes”

  22. Coping With Metastability (Cont’d) “For the synchronous designer the problem is that metastability may persist beyond the time interval that has been allocated to recover from potential metastability. It is simply not possible to obtain a decision within a bounded length of time. The asynchronous designer, on the other hand, will eventually obtain a decision, but there is no upper limit on the time he will have to wait for the answer. In [22] the terms “time safe” and “value safe” are introduced to denote and classify these two situations.” • [22] D.M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University, October 1984. J. SPARSØ, S. FURBER (Editors), “PRINCIPLES OF ASYNCHRONOUS CIRCUIT DESIGN – A Systems Perspective”, pp. 78

  23. Coping With Metastability (Cont’d) • A traditional Timing-Safe method • Using 2 flip-flop synchronizer • MTBF… Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  24. SoC Communication Infrastructure Architectures • Point-to-Point, • Bus, Ring, Crossbar, Network T. Bjerregaard, S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip”, 2006

  25. GALS Design Style Taxonomy GALS in its universal definition classifying GALS design styles according to the methods they use to transfer data between timing domains (Data Synchronizing and Communicating Methods ) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  26. GALS Design Style Taxonomy (Cont’d) • The pausible-clock design style • Relies on locally generated clocks • That can be stretched or paused • Either to prevent metastability • Or to let a transmitter or receiver stall because of a full or empty channel. • A ring oscillator typically generates the clocks. • The Integrated Systems Laboratory at ETHZ (Swiss Federal Institute of Technology Zurich) • Has implemented several chips featuring pausible clocks, including a cryptography chip. • Special wrapper circuits interface between synchronous blocks, such that each wrapper includes a pausible-clock generator. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  27. GALS Design Style Taxonomy (Cont’d) • The asynchronous design style • Involves the general case in which no timing relationship between the synchronous clocks is assumed. • Are maximally flexible with respect to timing. • Fulcrum Microsystems’ Nexus architecture includes an asynchronous crossbar switch that handles communication between blocks operating at arbitrary clock frequencies. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  28. GALS Design Style Taxonomy (Cont’d) • The loosely synchronous design style • Is for cases in which there is a well-defined, dependable relationship between clocks. • It’s possible to • Exploit the stability of these clocks to achieve high efficiency • While simultaneously providing tolerance for the large amounts of skew inherent in global interconnects. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  29. GALS Design Style Taxonomy (Cont’d) • The loosely synchronous design style • Mesochronous • The sender and receiver operate at exactly the same frequency with an unknown yet stable phase difference. • Intel’s 80-core processor employs a mesochronous design. It uses synchronous tiles and a skew-tolerant networkon-chip (NoC) interconnect scheme driven by one stable global clock. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  30. GALS Design Style Taxonomy (Cont’d) • The loosely synchronous design style • Plesiochronous • The sender and receiver operate at the same nominal frequency but may have a slight frequency mismatch, such as a few parts per million, which leads to drifting phase. • Gigabit Ethernet is a common example. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  31. GALS Design Style Taxonomy (Cont’d) • The loosely synchronous design style • Heterochronous • The sender and receiver operate at nominally different clock frequencies. • Ratiochronous • rationally related clock frequencies in which the receiver’s clock frequency is an exact rational multiple of the sender’s, • and both are derived from the same source clock • such that there is a predictable periodic phase relationship. • Nonratiochronous Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  32. GALS Design Style Taxonomy (Cont’d) • In the next slides, • We describe a simplified example that provides one-way communication between transmitter and receiver blocks. • The blocks • operate synchronously using two different clocks • and are connected together using a FIFO buffer that is robust and free of metastability. • The FIFO buffer can have almost any capacity, including just one data item, • but this may affect throughput. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  33. GALS Design Style Taxonomy (Cont’d) • In the next slides, • To send a data item, • the transmitter asserts put and drives data_in. • The FIFO buffer accepts the data on the rising edge of put and lowers ok_to_put. • If this operation fills the FIFO buffer, ok_to_put remains low until some data is removed. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  34. GALS Design Style Taxonomy (Cont’d) • In the next slides, • On the receiver side, • the FIFO buffer asserts ok_to_take when data is available. • To remove a data item, the receiver latches data_out and asserts take. • The FIFO buffer lowers ok_to_take until new data is available. • If the FIFO buffer is empty, ok_to_take remains low until new data is inserted. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  35. Pausible Clock GALS Design Style • The Chapiro’s GALS approach • using pausible clocks to enable separate clock domains to communicate without metastability. • each locally synchronous block generates its own clock with a ring oscillator. • Each ring oscillator’s period is set according to the speed requirements of the block it drives. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  36. Pausible Clock GALS Design Style (Cont’d) • Pausible or pausable • Has various modified and customized versions • Stoppable • Stretchable • Data-driven • …

  37. Pausible Clock GALS Design Style (Cont’d) • Two potential advantages of pausible clocking • Robustness • Pausing delays a clock’s sampling edge until after the arrival of data from the other domains, thus avoiding metastability altogether. • Power • Pausing the clock of a block awaiting communication prevents that block from dissipating dynamic power. • Presumably, VDD can be lowered during prolonged stalls to reduce static power as well. • Hence, this style may be useful in power-critical designs. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  38. Pausible Clock GALS Design Style (Cont’d) • From designers viewpoint • Simplifying design reuse • By encapsulating crucial timing constraints in the clock generator wrappers. • By controlling the receiver’s clock, these interfaces ensure that data arriving at the receiver satisfies the receiver’s timing requirements, thus completely avoiding metastability. • Once this interface wrapper IP has been verified, it can be reused for many different local blocks without the need for further timing analysis. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  39. Pausible Clock GALS Design Style (Cont’d) • From designers viewpoint • Clock tree latency • Must be considered in GALS designs. • If the latency to distribute a clock is larger than a single clock cycle, invalid operations may occur after the clock was supposed to have stopped. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  40. Pausible Clock GALS Design Style (Cont’d) • From designers viewpoint • Designing ring oscillators for robustness and good performance • A major difficulty in some GALS research • The clock period can have high jitter, varying significantly from cycle to cycle as it restarts from a pause. • This jitter can be amplified by the clock distribution network, further cutting into the timing margin. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  41. Pausible Clock GALS Design Style (Cont’d) • From designers viewpoint • A potential advantage of ring oscillator clocks is • That variations in the clock period should track variations in logic-gate delays across a range of operating conditions. • Unfortunately, standard CAD tools do not account for this behavior during analysis, and they might force conservative, worst-case designs. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  42. Pausible Clock GALS Design Style (Cont’d) Pausible-clock GALS design style: circuit (a) and timing diagram (b) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  43. Pausible Clock GALS Design Style (Cont’d) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  44. Pausible Clock GALS Design Style (Cont’d) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  45. Asynchronous Interface GALS Design Style • Uses circuits known as synchronizers • to transfer signals arriving from an outside timing domain to the local timing domain. • Although simple asynchronous interfaces suffer from low throughput, • This limitation can be overcome with careful designs. Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  46. Asynchronous Interface GALS Design Style (Cont’d) Asynchronous GALS design style employing synchronizers: circuit (a) and timing diagram (b) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  47. Asynchronous Interface GALS Design Style (Cont’d) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  48. Asynchronous Interface GALS Design Style (Cont’d) Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  49. Asynchronous Interface GALS Design Style (Cont’d) • This simplistic design can transfer at most • One datum for every three cycles of transmitter clock φT or receiver clock φR • whichever is slower Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

  50. Asynchronous Interface GALS Design Style (Cont’d) • From designers viewpoint • Offering the most flexibility and probably the easiest integration into existing CAD flows Paul Teehan, et al., “A Survey and Taxonomy of GALS Design Styles”, IEEE 2007

More Related