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Data Flow Modeling in VHDL

ECE 545 Lecture 7. Data Flow Modeling in VHDL. R equired reading. P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL. Types of VHDL Description. dataflow. VHDL Descriptions. Testbenches. behavioral (sequential).

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Data Flow Modeling in VHDL

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  1. ECE 545 Lecture 7 Data Flow Modelingin VHDL

  2. Required reading • P. Chu, RTL Hardware Design using VHDL • Chapter 4, Concurrent Signal Assignment • Statements of VHDL

  3. Types of VHDL Description dataflow VHDL Descriptions • Testbenches behavioral(sequential) structural Components and interconnects Concurrent statements Sequential statements • Registers • State machines • Instruction decoders Subset most suitable for synthesis

  4. Synthesizable VHDL Dataflow VHDL Description VHDL code synthesizable Dataflow VHDL Description VHDL code synthesizable

  5. Register Transfer Level (RTL) Design Description Combinational Logic Combinational Logic Today’s Topic … Registers

  6. Data-Flow VHDL Concurrent Statements • simple concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when)

  7. Simple concurrent signal assignment <= target_signal <= expression;

  8. Conditional concurrent signal assignment When - Else target_signal <= value1whencondition1else value2whencondition2else . . . valueN-1whenconditionN-1else valueN;

  9. Selected concurrent signal assignment With –Select-When withchoice_expressionselect target_signal <= expression1whenchoices_1, expression2whenchoices_2, . . . expressionNwhenchoices_N;

  10. Data-Flow VHDL Concurrent Statements • simple concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when)

  11. Wires and Buses ECE 448 – FPGA and ASIC Design with VHDL

  12. Signals SIGNALa : STD_LOGIC; SIGNALb : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1 wire b bus 8

  13. Merging wires and buses a 4 10 b 5 d = a || b || c c SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); d <=

  14. Merging wires and buses a 4 10 b 5 d = a || b || c c SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); d <= a & b & c;

  15. Splitting buses a = d .. 4 10 d b = d .. 5 c = d SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); a <= b <= c <=

  16. Splitting buses a = d9..6 4 10 d b = d5..1 5 c = d0 SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNALc: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); a <= d(9 downto 6); b <= d(5 downto 1); c <= d(0);

  17. Data-flow VHDL: Example x y s cin cout

  18. Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (x : IN STD_LOGIC ; y: IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ;

  19. Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ; equivalent to ARCHITECTURE dataflow OF fulladd IS BEGIN cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; s <= x XOR y XOR cin ; END dataflow ;

  20. Logic Operators • Logic operators • Logic operators precedence and or nand nor xor not xnor only in VHDL-93 or later Highest not and or nand nor xor xnor Lowest

  21. No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ;

  22. arith_result <= a + b + c – 1; Chapter 4

  23. Signal assignment statement with a closed feedback loop • a signal appears in both sides of a concurrent assignment statement • E.g., q <= ((notq) and (not en)) or (d and en); • Syntactically correct • Form a closed feedback loop • Should be avoided Chapter 4

  24. Data-Flow VHDL Concurrent Statements • simple concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when)

  25. Conditional concurrent signal assignment When - Else target_signal <= value1whencondition1else value2whencondition2else . . . valueN-1whenconditionN-1else valueN;

  26. Most often implied structure Value N … Value N-1 Target Signal Value 2 Value 1 Condition N-1 Condition 2 Condition 1 When - Else target_signal <= value1whencondition1else value2whencondition2else . . . valueN-1whenconditionN-1else valueN; F T .… F T F T

  27. 2-to-1 “abstract” mux • sel has a data type of boolean • If sel is true, the input from “T” port is connected to output. • If sel is false, the input from “F” port is connected to output. Chapter 4

  28. Chapter 4

  29. Chapter 4

  30. Chapter 4

  31. E.g., Chapter 4

  32. E.g., Chapter 4

  33. Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all;

  34. Operators • Relational operators • Logic and relational operators precedence = /= < <= > >= Highest not = /= < <= > >= and or nand nor xor xnor Lowest

  35. Priority of logic and relational operators compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else …

  36. Data-Flow VHDL Concurrent Statements • simple concurrent signal assignment () • conditional concurrent signal assignment • (when-else) • selected concurrent signal assignment • (with-select-when)

  37. Selected concurrent signal assignment With –Select-When withchoice_expressionselect target_signal <= expression1whenchoices_1, expression2whenchoices_2, . . . expressionNwhenchoices_N;

  38. Most Often Implied Structure With –Select-When withchoice_expressionselect target_signal <= expression1whenchoices_1, expression2whenchoices_2, . . . expressionNwhenchoices_N; choices_1 expression1 expression2 choices_2 target_signal expressionN choices_N choice expression

  39. Allowed formats of choices_k WHEN value WHEN value_1 | value_2 | .... | value N WHEN OTHERS

  40. Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", c WHEN "001" | "111", d WHEN OTHERS;

  41. Syntax • Simplified syntax: with select_expression select signal_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3, . . . value_expr_n when choice_n; Chapter 4

  42. select_expression • Discrete type or 1-D array • With finite possible values • choice_i • A value of the data type • Choices must be • mutually exclusive • all inclusive • others can be used as last choice_i Chapter 4

  43. E.g., 4-to-1 mux Chapter 4

  44. Can “11” be used to replace others? Chapter 4

  45. E.g., 2-to-22 binary decoder Chapter 4

  46. E.g., simple ALU Chapter 4

  47. E.g., Truth table Chapter 4

  48. Conceptual implementation • Achieved by a multiplexing circuit • Abstract (k+1)-to-1 multiplexer • sel is with a data type of (k+1) values:c0, c1, c2, . . . , ck Chapter 4

  49. select_expression is with a data type of 5 values: c0, c1, c2, c3, c4 Chapter 4

  50. Chapter 4

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