1 / 17

ECE 424 Design of Microprocessor-Based Systems

ECE 424 Design of Microprocessor-Based Systems. Fundamentals of Digital Logic and Binary Number Representation. Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901. X. Y = X. X. Z = X  Y. Y. X Y Z 0 0 0 0 1 0 1 0 0 1 1 1. X Y 0 0 1. X. Z = X  Y.

dot
Download Presentation

ECE 424 Design of Microprocessor-Based Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. ECE 424 Design of Microprocessor-Based Systems Fundamentals of Digital Logicand Binary Number Representation Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

  2. X Y = X X Z = X  Y Y X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 • X Y • 0 • 0 1 X Z = X  Y Y Digital Signals and Basic Logic Gates • Digital signal values True 1 High Voltage (e.g. 5V)12 False 0 Low Voltage (e.g. 0V) • Basic logic gates 1. Inverter Truth Table of an inverter 2. AND Truth Table of an AND gate 3. NAND

  3. X Z = X + Y Y X Z = XY +XY Y Z = X + Y Z = X + Y X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 X Z = XY +XY Y Basic Logic Gates X 4. OR Z = X + Y Y Truth Table of an OR gate 5. NOR 4. XOR Truth Table of an XOR gate 5. XNOR

  4. I O C • C I O • X Z • 0 0 0 • 0 1 1 I1 X Y O I2 C S 2-to-1 multiplexer Bi-direction circuit Basic Logic Gates • Tri-state Buffer Truth table of a tri-state buffer Mux

  5. Decoder X Y Z1 Z2 Z3 Z4 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 X Z1 (00) N inputs 2N outputs   Z2 (01) Z3 (10) Y Z4 (11) Decoder Circuits • A decoder circuit uniquely selects one of its outputs according to its input signals • 2-to-4 decoder implementation

  6. X Y X CS X Y Y CS Z X Y CS Decoder Circuit • 3-to-8 decoder implementation • Assume that we have 2-to-4 decoders available as standard components • When CS is low (0), all the outputs of the decoder are low (0) 2-to-4 decoder

  7. D CLK D Q Q Q CLK D D Q CLK Q CLK Q Sequential Logic Circuits • D latch • When CLK=1, Q always reflects the signal value at input D • If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0 • D Flip-flop • D flip-flop will not change its output values unless there is a negative edge event at CLK input (CLK switches from logic 1 to 0). • When a negative edge appears at CLK input , D Flip-flop updates Q to the current D value

  8. Clk C B A Init. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C DFF DFF DFF Q Q Q D D D Q Q Q CLK B C A DFF DFF Q Q Q D D D Q Q Q CLK Sequential Logic Circuits • Counter • Basic binary counter • Synchronous counter

  9. DFF DFF Q Q D D CLK_4 Q Q CLK CLK DFF DFF CLK_3 Q Q D D CLK_3 Q Q CLK Sequential Logic Circuits • frequency divider • Divide clock frequency by 4 CLK CLK_4 • Divide clock frequency by 3

  10. Q3 Q2 Q1 Q0 DFF DFF DFF DFF Q Q Q Q D D D D Q Q Q Q Data CLK Q3 Q2 Q1 Q0 DFF DFF DFF DFF 0 Q Q Q Q D D D D Q Q Q Q CLK Sequential Logic Circuits • Register • A row of storage elements (e.g. D flip-flops) Q[3:0] • Shift register CLK Q3 Q2 Q1 Q0 Init. 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0

  11. N/2 bit address Memory location  Row decoder   Column decoder  N/2 bit address Memories Circuits • Memories are storage devices containing a large number of storage locations • Addressing space: total number of memory locations • If a memory device has N bit addresses, it has 2N memory locations

  12. Memory Types • ROM v.s. RAM • ROM: Read-Only Memory • RAM: Random Access Memory (allow both read and write operations) • Volatile v.s. Non-volatile • Volatile: memory loses data after power is off • Non-volatile: memory keep stored data even after power is off Non-volatile Volatile

  13. 1K 1K CS CS Addr[9:0] Addr[10] W/R W/R W/R Memory Addressing • Example • Use memory chips with the capacity of 1K (1024 bit) to construct a 2K memory system

  14. Binary Decimal 1011  1*2^3 + 0*2^2 + 1*2^1 + 1*2^0 = 11 0111  0*2^3 + 1*2^2 + 1*2^1 + 1*2^0 = 7 1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 F A 3 5 Binary Number System • Converting binary numbers to decimal numbers • Converting binary numbers to hexadecimal numbers

  15. A B 0 1 0 1 + 1 0 0 1 Full adder C_in C_out 1 1 1 0 S A[0] B[0] A[1] B[1] A[2] B[2] A[3] B[3] Full adder Full adder Full adder Full adder C_out C_in C_0 C_1 C_2 S[3] S[0] S[1] S[2] Binary Addition • Example • A single-bit full adder • 4-bit adder

  16. 1’s complement Decimal 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 1 1 0 1 1 0 -1 1 0 1 -2 1 0 0 -3 Handling Negative numbers • Signed magnitude Signed magnitude Decimal 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 0 1 0 1 -1 1 1 0 -2 1 1 1 -3 • The left-most bit is a sign bit 0 indicates positive a number and 1 indicates negative a number • One’s complement • For positive number A, it is represented as usual binary number • For negative number -A, its representation is obtained by flipping the bits of the binary representation of A

  17. 2’s complement Decimal 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 1 1 -1 1 1 0 -2 1 0 1 -3 1 0 0 -4 0 1 1 + 1 1 1 1 0 1 0 0 1 0 + 1 0 1 1 1 1 3  1 2 2  3 -1 Overflow Ignore 2 -1 Handling Negative numbers • Two’s complement • For positive number A, it is the same as the one’s complement • For negative number A, add one to the one’s complement representation • By using two’s complement number representation, minus operations can be performed by adders

More Related