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Simulated-Annealing-Based Solution. By Gonzalo Zea s031418 Shih-Fu Liu s031003 . Agenda. Hardware Allocation Problem Input Description Basic Allocation Problem Subproblem Formulation of the entire data path synthesis problem Cost Table Conditional Resource Sharing

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Simulated annealing based solution l.jpg

Simulated-Annealing-Based Solution

By

Gonzalo Zea s031418

Shih-Fu Liu s031003


Agenda l.jpg
Agenda

  • Hardware Allocation Problem

    • Input Description

    • Basic Allocation Problem

    • Subproblem

    • Formulation of the entire data path synthesis problem

    • Cost Table

    • Conditional Resource Sharing

  • Simulated-Annealing-Based Solution

    • Generating New States

    • Stopping criteria

    • Cost function

    • Constraints

    • Delays

  • Loops

  • Result of example

  • Synthesizing Pipelined Data Paths

  • Conclusions

– Agenda – Hardware Allocation Problem

Simulated-Annealing-Based Solution


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Hardware Allocation Problem

  • execution speed of the data path (T)

  • total hardware cost of the data path (C)

  •  f(T,C) should be minimized

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Input Description

  • Code sequence where parallelism, sequentiality, and disjointness (mutually exclusive operations) are explicitly stated

  • Compilerlike optimization techniques (e.g. dead code elimination, constant folding)

  • Disjointness is a result of the conditional clauses in the input description

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Basic Allocation Problem

  • given description allocate into a minimum number of registers

  • Arithmetic unit allocation

    • entails scheduling operations

    • minimum numbers of ALU’s

    • meeting cost or timing constraints

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Subproblem

  • Abolish fixed code sequence  gaining an extra degree of freedom

  • Disjoint variables share the same register

  • Precedence constraints must be met

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Formulation of the entire data path synthesis problem

  • C = p1 * (#alu) + p2 * (exec_time) + p3 * (#register) + p4 * (#bus)

    • p1, p3, p4 … area parameters

    • p2 … execution time parameter

  • By meeting constraints and being minimal, C is optimal

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Cost Table

  • Register cost

    • Equal to the area of the library register cost

  • Costs of ALU operations

    • non linear function

  • Estimating interconnecting area

    • Complex function of the number of registers and ALU’s in the data path

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Conditional Resource Sharing

  • Disjoint statements can exist on top of each other on the same time-space slot  resource sharing

Agenda – Hardware Allocation Problem – Simulated-Annealing-Based Solution

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

  • Basic algorithm

    • Random generation of new states

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

  • Acceptance rule of the generated states depending on the temperature T

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

  • Number of states generated influences quality and can be defined by user

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

  • Most important points

    • Generation of new states

    • Optimization of the cost function

Simulated-Annealing-Based Solution


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Generating New States

  • Interchanging two code operations

  • Displacing a code operation from one location to another

  • Interchanging variables in a symmetric operation

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Generating New States cont’d

  • High Temperature

    • Two numbers (a, b) randomly generated

    • If (b < number of operations)

      • Interchanging two operations

        • Violate constraints  variables are interchanged

    • If (b > number of operations)

      • New random location is generated

        • If not violate constraints

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Generating New States cont’d

  • Low Temperature

    • Two numbers (a, b) randomly generated

    • If (b < number of operations)

      • Interchanging neighboring operations

        • Violate constraints  variables are interchanged

    • If (b > number of operations)

      • Displacement with neighboring operations in time or space slots in random order

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Stopping Criteria

  • Cost function stays the same for three temperature points.

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Cost function

  • Depends on

    • Number of registers

    • Interconnection costs

      • Links

      • Buses

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Constraints

  • Hardware Resource

    • Number of ALU’s & Registers

  • Execution Time

Hardware Allocation Problem – Simulated-Annealing-Based Solution – Loops

Simulated-Annealing-Based Solution


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Delays

  • Highest common factor of all different operation delays equals one time frame

  • Interchanges or displacements of operations affects the time position

Simulated-Annealing-Based Solution – Loops – Synthesizing Pipelined Data Paths

Simulated-Annealing-Based Solution


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Loops

space

  • Unwinding depends on disjointness

  • Improving of execution time

Simulated-Annealing-Based Solution – Loops – Synthesizing Pipelined Data Paths

time

Simulated-Annealing-Based Solution


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Results of Examples

  • HAL

    • Clock cycles : 17

    • Multipliers : 3

    • Adder : 3

Simulated-Annealing-Based Solution – Loops – Synthesizing Pipelined Data Paths

  • SAB-Solution

    • Clock cycles : 17

    • Multipliers : 2

    • Adder : 3

    • Calculation time increases quadratically

Simulated-Annealing-Based Solution


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Synthesizing Pipelined Data Paths

  • Pipelining

    • Inserting registers between logic modules

    • Increasing latency

    • Improving throughput

  • Pipeline Synthesis

    • Partitioning input data flow description into pipeline stages

    • Finding a placement of micro-operations within each stage for meeting constraints

Loops – Pipelined Data Paths - Conclusion

Simulated-Annealing-Based Solution


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Synthesizing Pipelined Data Paths

  • Algorithm

    • Serial pipeline schedule

      • Doesn’t violate delay constraints

      • If max. delay exceeded  separating into a new stage

      • Each stage placement problem is treated separately and afterwards summed up

Loops – Pipelined Data Paths - Conclusion

Simulated-Annealing-Based Solution


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Synthesizing Pipelined Data Paths

  • Algorithm

    • Interchanging and displacement

      • Moving operations within adjacent stages

      • Constraint violation allowed with penalization

        • Doesn’t appear in the final result

      • Displacing last phase operations to the empty stages

Loops – Pipelined Data Paths - Conclusion

Simulated-Annealing-Based Solution


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Synthesizing Pipelined Data Paths

  • Algorithm

    • Throughput

      • k … number of stages

      • di … delay of each stage

      • ρ … expected resynchronization rate

Loops – Pipelined Data Paths - Conclusion

Simulated-Annealing-Based Solution


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Conclusion

  • Entire allocation process  two-dimensional placement problem

  • Simultaneously cost-constrained allocation of hw resources and execution time

  • Trade-off hardware cost against execution speed

Pipelined Data Paths – Conclusion -

Simulated-Annealing-Based Solution


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Simulated-Annealing-Based Solution

By

Gonzalo Zea s031418

Shih-Fu Liu s031003