Development of Virtual FPGA lab and FPGA-based web browser

Development of Virtual FPGA lab and FPGA-based web browser Nina Drozd Supervisor: Fearghal Morgan Co-Supervisor: Martin Glavin

Existing Virtual FPGA Lab Features • Login and register facility (restricted) • Limited user interface • Upload user FPGA bit-stream file and configure FPGA • Access to example FPGA bit-stream files • Two counter examples • Applied VHDL bit-stream example and web-base I/O GUI (CSR r/w, SRAM r/w, image processing functions, USB interface)

Project Goals : Phase 1 • Development of virtual FPGA lab • Based on existing virtual lab • Enable virtual switch access • Provide remote lamp on/off • Enhance user interface • Develop account management and statistics generation • Incorporate feedback facility • Replacing Spartan-3 with Diligent Nexys module • Package and document the virtual FPGA lab LED (on when Program uploaded) Press to run program 4 buttons for user input Switches for user input

Project Goals : Phase 2 • Development of FPGA-based Web browser • Implement embedded processor, microcontrolled Linux on FPGA, with ethernet and user switches • Display (rolling) web pages: • Applied VHDL virtual lab • BIRC research group home page • FPGA-interest website • ‘FPGA technology intro and ‘What’s this system’ page

Further enhancements: • The example files collected into a table with an interactive ‘action’ button to configure the board • User’s uploaded files also collected into a table with ‘configure’ and ‘delete’ buttons • LED used to show the user that the board is reconfigured with a chosen bit-stream file • Switches on the board are shown in user interface and are interactive (user can virtually change switches) • Push buttons are also interactive (user can push a button on user interface, sending out the signal to the board so that physical configuration is changed) • Textbox displaying time elapsed during configuration of the board by bit-stream file • Latency test push button (to test the time period between initiation of board configuration and end of it)

Registration and Administration • Existing system: • The user is supplied with a hyperlink to server registration page, the information is then processed on the server and user added to database of users • Enhanced system: • User registration form is included in the webpage • User fills in information, if registration key is correct, a new user can now be added to database

Project Planning and Timescales • Phase 1 ‘Development of virtual FPGA lab’ major goals • Review existing virtual lab setup • Server (currently implemented across two servers) • Video and user I/O • Meet with developer (Frank Callaly) • Document the system • Port to single server • Draw up specification • Implement • Field test • Report

Project Planning and Timescales • Phase 2 ‘Development of FPGA-based web browser’ major goals • Specify FPGA-based web browser elements • Implement Microblaze and uCLinux on FPGA • Develop ethernet i/f • Develop web access sequence • Display to monitor • Include user page selection

Development of Virtual FPGA lab and FPGA-based web browser

Development of Virtual FPGA lab and FPGA-based web browser

Presentation Transcript

Cryptanalysis on FPGA Based Hardware

Lab 4: FPGA Implementation

Design and development of FPGA based PCI Express card

Future FPGA Development

FPGA

Security of FPGA

FPGA Based Smoke Simulator

FPGA-Based Arcade Emulation

FPGA

FPGA based RFID Reader

SRAM-based FPGA

Software for development and communication with FPGA based hardware

FPGA

FPGA

Communication Between FPGA and LabView - FPGA part

FPGA

FPGA System Development

Introduction to FPGA Development

FPGA

FPGA-Based Arcade Emulation

FPGA Editor Lab Introduction

FPGA-based compute nodes