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ELEC 2200-002 Digital Logic Circuits Fall 2008 Logic Synthesis (Chapters 2-5). Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu. Logic Synthesis.

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elec 2200 002 digital logic circuits fall 2008 logic synthesis chapters 2 5

ELEC 2200-002Digital Logic CircuitsFall 2008Logic Synthesis (Chapters 2-5)

Vishwani D. Agrawal

James J. Danaher Professor

Department of Electrical and Computer Engineering

Auburn University, Auburn, AL 36849

http://www.eng.auburn.edu/~vagrawal

vagrawal@eng.auburn.edu

ELEC2200-002 Lecture 6

logic synthesis
Logic Synthesis
  • Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured:
      • Performance – meets delay specification, or has minimum delay.
      • Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors.
      • Power – meets power specification, or consumes minimum power.
      • Testablility – has no redundant (untestable) logic and is easily testable.

ELEC2200-002 Lecture 6

synthesis procedure
Synthesis Procedure
  • Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit.
  • Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms:
      • Programmable logic array (PLA)
      • Standard cell library
      • Field programmable gate array (FPGA)
      • Other . . .

ELEC2200-002 Lecture 6

references on synthesis
References on Synthesis
  • G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.
  • S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.

ELEC2200-002 Lecture 6

programmable logic array pla
Programmable Logic Array (PLA)
  • A direct implementation of multi-output function as a two-level circuit in MOS technology.
  • PLA styles:
      • NAND-NAND
      • NOR-NOR
  • Textbook, Chapter 5.

ELEC2200-002 Lecture 6

example two output function
Example: Two-Output Function

Need four products: P1, P2, P3, P4

F1

A

F2

A

D

D

C

C

B

B

ELEC2200-002 Lecture 6

two level and or implementation
Two-Level AND-OR Implementation
  • Also known as technology-independent circuit.

INPUTS

AND

OR

C

P1

F1

P2

A

P3

F2

B

P4

D

ELEC2200-002 Lecture 6

nand nand implementation
NAND-NAND Implementation

INPUTS

NAND

NAND

C

F1

A

F2

B

D

ELEC2200-002 Lecture 6

a nand gate in mos technology
A NAND Gate in MOS Technology

VDD

VDD

VDD

XY

XY

XY

X

X

X

Y

Y

Y

GND

GND

GND

R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design,

Boston: McGraw-Hill, 2008, Section 6.8.2.

ELEC2200-002 Lecture 6

nand nand pla
NAND-NAND PLA

A

B

C

D

F1

F2

VDD

VDD

VDD

VDD

VDD

VDD

GND

ELEC2200-002 Lecture 6

nand nand pla schematic
NAND-NAND PLA SCHEMATIC

A

B

C

D

F1

F2

INPUTS

OUTPUTS

AND-plane

OR-plane

ELEC2200-002 Lecture 6

standard cell design
Standard-Cell Design
  • Obtain two-level minimized form.
  • Map the design onto predesigned building blocks called standard cells (technology mapping).
  • Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology:
      • 90 nanometer CMOS
      • 65 nanometer CMOS
      • 45 nanometer CMOS
      • . . .
  • This is known as application-specific integrated circuit (ASIC).

ELEC2200-002 Lecture 6

technology mapping
Technology Mapping
  • Find a common logic elements, e.g., two-input NAND gate and inverter.
  • MSOP is converted into NAND-NAND circuit.
  • Split gates into library cells, two-input NAND gates and inverters.
  • Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching).

ELEC2200-002 Lecture 6

a typical cell library
A Typical Cell Library

S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill

1994, Section 7.7, pp. 185-198.

ELEC2200-002 Lecture 6

nand3 cell
NAND3 Cell

Directed Acyclic

Graph (DAG)

(tree)

ELEC2200-002 Lecture 6

nand4 cell
NAND4 Cell

ELEC2200-002 Lecture 6

aoi21 cell
AOI21 Cell

ELEC2200-002 Lecture 6

oai21 cell
OAI21 Cell

ELEC2200-002 Lecture 6

aoi22 cell
AOI22 Cell

ELEC2200-002 Lecture 6

xor cell
XOR Cell

ELEC2200-002 Lecture 6

technology mapping procedure
Technology Mapping Procedure
  • Obtain MSOP.
  • Convert to two-level AND-OR circuit.
  • Transform to two-level NAND-NAND circuit.
  • Transform to two-input NAND and inverter tree network.
  • Perform an optimal pattern matching to obtain a minimum cost tree covering.

ELEC2200-002 Lecture 6

previous example 2 level nand
Previous Example: 2-Level NAND

INPUTS

NAND

NAND

C

F1

A

F2

B

D

ELEC2200-002 Lecture 6

circuit is a directed acyclic graph dag
Circuit is a Directed Acyclic Graph (DAG)

C

F1

A

F2

B

Each node is a

NAND gate.

D

ELEC2200-002 Lecture 6

splitting into a forest of trees
Splitting into a Forest of Trees

C

F1

D

B

C

D

A

F2

B

A

D

ELEC2200-002 Lecture 6

splitting dag into trees forest
Splitting DAG into Trees (Forest)

C

D

F1

C

B

D

A

B

F2

A

D

ELEC2200-002 Lecture 6

a simple technology mapping
A Simple Technology Mapping

NAND2 (3)

NAND2 (3)

C

(2)

F1

D

B

C

D

NAND3 (4)

NAND3 (4)

A

F2

B

(2)

A

Cost = 24

D

NAND2 (3)

ELEC2200-002 Lecture 6

two input nand trees
Two-Input NAND Trees

C

F1

D

B

C

D

A

F2

B

A

D

ELEC2200-002 Lecture 6

alternatively in graph format
Alternatively, in Graph Format

C

D

F1

B

C

D

A

F2

B

A

D

ELEC2200-002 Lecture 6

an improved technology mapping
An Improved Technology Mapping

C

OAI21 (4)

D

(2)

F1

Inverter inserted

For pattern matching

B

NAND3 (4)

C

D

NAND3 (4)

A

F2

B

(2)

NAND2 (3)

A

Cost = 22

D

NAND2 (3)

ELEC2200-002 Lecture 6

alternatively in graph format30
Alternatively, in Graph Format

C

OAI21 (4)

D

F1

(2)

Inverter inserted

For pattern matching

B

NAND3 (4)

C

D

NAND3 (4)

NAND2 (3)

A

F2

B

(2)

A

D

NAND2 (3)

Cost = 22

ELEC2200-002 Lecture 6

original reference
Original Reference
  • K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc.24th Design Automation Conf., 1987, pp. 341-347.

ELEC2200-002 Lecture 6