Ayas Kanta Swain , Assistant Professor, ECE Dept ., NIT Rourkela

1. SystemVerilog Data Types Ayas Kanta Swain, Assistant Professor, ECE Dept., NIT Rourkela

2. Why was SystemVerilog Created • In late 1990s, the Verilog became the most widely used language for describing hardware for simulation and synthesis. • Initial versions had only simple constructs for creating tests. • As design sizes outgrew the verification capabilities of the language, commercial Hardware Verification Languages (HVLs) such as OpenVera and e were created. • Companies that did not want to pay for these tools instead spent hundreds of man-years creating their own custom tools. • This productivity crisis, along with a similar one on the design side, led to the creation of Accellera, a consortium of EDA companies and users who wanted to create the next generation of Verilog. • The donation of the OpenVera language formed the basis for the HVL features of SystemVerilog. Accellera’s goal was met in November 2005 with the adoption of the IEEE standard 1800-2005 for SystemVerilog, IEEE (2005). • In December 2009, the latest Verilog LRM, 1364- 2005, was merged with the aforementioned 2005 SystemVerilog standard to create the IEEE standard 1800-2009 for SystemVerilog. Merging these two standards into a single one means there is now one language, SystemVerilog, for both design and verification.

3. Typical features of an HVL Some of the typical features of an HVL that distinguish it from a Hardware Description Language such as Verilog or VHDL are: • Constrained-random stimulus generation • Functional coverage • Higher-level structures, especially Object-Oriented Programming, and transaction level modeling • Multi-threading and interprocesscommunication (IPC) • Support for HDL types such as Verilog’s 4-state values • Tight integration with event-simulator for control of the design • These allow you to create test benches at a higher level of abstraction than you are able to achieve with an HDL or C.

4. Data Types • SystemVerilog introduces new data types with the following benefits • Two-state: better performance, reduced memory usage • Queues, dynamic and associative arrays: reduced memory usage, built-in support for searching and sorting • Classes and structures: support for abstract data structures • Unions and packed structures: allow multiple views of the same data • Strings: built-in string support • Enumerated types: code is easier to write and understand

5. Built-In Data Types • Verilog-1995 has two basic data types: 4-state values: 0, 1, Z, and X. • Variables used to store combinational and sequential values. • Unsigned single or multi-bit (reg [7: 0] m), • Signed 32-bit variables (integer), • Unsigned 64-bit variables (time), and • Floating point numbers (real). All storage is static, meaning that all variables are alive for the entire simulation and routines cannot use a stack to hold arguments and local values. • Net is used to connect parts of a design such as gate primitives and module instances. • Nets used as scalar and vector wires to connect together the ports of design blocks. • System Verilog adds many new data types to help both hardware designers and verification engineers.

6. System Verilog Data Types

7. How to Comment // Thisis a one-line comment /* Thisis a multiple line comment. Sincethis line iswithintheblock comment symbols, itis a comment. */ Block cannot be insideothers.

8. The Logic Type • In Verilog ,we always the difference between a reg and a wire. • When driving a port, which should you use? How about when you are connecting blocks? System Verilog: • Classic reg data type-Continuous assignments, gates, and modules, in addition to being a variable.  logic (to avoid look like to register). • A logic signal can be used anywhere a net or regis used, Exception: • A logic variable cannot be driven by multiple structural drivers (bidirectional bus). • System Verilog uses net-type to resolve the multiple values to determine the final value.

9. Example

10. 2-State Data Types System Verilog introduces several 2-state(value) data types: • To improve simulator performance and • Reduce memory usage, (Compared 4-state types). Ex- Situation in network packet header that contains a valid address. No need of 4-state values. 4-state converted to 2-state value: X and Z becomes ‘0’ The simplest type is the bit , which is always unsigned. There are four signed 2-state • types: byte, shortint,int, and longint. Don’t use signed type in unsigned type. (Unsigned from 0-255)

11. Example-bit

12. 2-state-Integer • Integer are the whole number without fraction. (By default signed) • // ubyteisconverted to signedtype and assigned to sisi = signed'(ubyte);

13. 2-state Integer unsigned • Use “unsigned” type

14. 2-State byte(8-bit Signed)

15. Data Type-String • String data type is a ordered collection of data. Syntax stringvariable_name [= initial_value]; • Variable_name is a identifier, optional initial value is a string literal. “” empty string (if nothing specify) .Strings can be updated during simulation.(In Verilog it is fixed)

16. String in Verilog • An ASCII character is 8-bit. To store string we require no. of bytes – no. of character (variable length strings. Each character is 1 byte) String Operators

17. String Methods • String methods are the functions to work with strings.

18. Example-String Method See String Conversion Method

19. SystemVerilog Arrays System Verilog can build complicated data structure using different types of arrays. • Static Arrays • Dynamic Arrays • Associative Arrays • Queues Static Arrays: An arrays whose size is known before compilation. Packed: bit [2:0][7:0] m_data; and UnPacked array: bit [15:0] m_mem [10:0];

20. Packed Arrays • Packed arrays are the dimensions declared before the variable name. bit [3:0] data; // Packedarrayor vector 1D PackedArray

21. Packed Arrays Multidimensional packed arrays segmented into smaller group. Use: You may want both to access the entire value and also to divide it into smaller elements. 2D packed arrays with 32 bits or 4 bytes.

22. Packed Arrays 3D Packed Array:

23. UnPacked Arrays Unpacked array declares the dimension after the variable. Fixed size arrays, Dynamic Arrays, Associated Arrays and queues. 1D Unpacked Array:

24. UnPacked Array Multidimensional Unpacked array:

25. Packed+Unpacked Array

26. Dynamic Array • Dynamic array size is not known during compilation. • It can be defined or changed as needed during run time. • It specified by empty square brackets. [ ] Syntax: [data_type] [identifier_name] []; bit [7:0] stack []; // A dynamicarray of 8-bit vector stringnames []; // A dynamicarraythat can containstrings A New() functionisused to allocatethesize of anarray and initialseitselement.

27. Dynamic Array

28. Associative Arrays • Associative array stores contains with a certain key inside [ ]

29. Queues • This data type allows to push data into the queue or pop from the array. (Recognized by $ inside a [ ]) • It uses First In First Out scheme. • It is a 1D unpack array.

30. Structure Structure contains element of different data types as compared to arrays that contains data of same type. It can be as a whole given an individual name. Syntax:

31. Structure

32. Typedef USer-defined data type

33. References • Chris Spear, “System Verilog for Verification: A Guide to Learning the Testbench Language Features”, Springer US, 2008 • Verificationexcellence. Usefedora.com • Chipverify.com • https://www.verificationguide.com/p/systemverilog-tutorial.html • http://www.asic-world.com/systemverilog/tutorial.html • http://www.testbench.in/SV_00_INDEX.html