Efficient Technology Mapping Algorithm for Routing Congestion Under Delay Constraints

1. An Efficient Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints Prashant Saxena Synopsys Inc Hillsboro, OR 97124 Rupesh S. Shelar Intel Corporation Hillsboro, OR 97124 Xinning Wang Intel Corporation Hillsboro, OR 97124 Sachin S. Sapatnekar University of Minnesota Minneapolis, MN 55455 International Symposium on Physical Design San FranciscoApril 5, 2005

2. Outline • Introduction • Algorithm Overview • Congestion Map Generation • Slack-constrained Covering • Results & Conclusion

3. Motivation • Technology Scaling • Routing resources growing at same rate? • Upper metal layers for global signals • Resistive (i.e., wide) wires • Result: Routing Congestion

4. Design Freedom Targeting Routing Congestion RTL Technology Mapping Placement Routing • Can be alleviated during routing,placement,technology mapping, and logic synthesis • Limited flexibility during P & R points to technology mapping • Mapping decides wires

5. Previous Work • Structural logic synthesis • Adhesion metric, Kudva et al.,TCAD’03 • Computationally expensive • Congestion-aware Technology Mapping using • Wirelength, Stok et al.,ICCAD’01, Pandini et al.,TCAD’03 • “ … a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking.’’ • Mutual contraction (MC), Liu et al., ISPD’05 • Predictive probabilistic congestion, Shelar et al., TCAD’05 • Congestion map based on subject graph

6. Outline • Introduction • Algorithm Overview • Congestion Map Generation • Slack-constrained Covering • Results & Conclusion

7. Problem Definition • Minimize routing congestion under delay constraints during technology mapping • Dynamic programming for delay constraints • Routing congestion: captured by track overflow and max. congestion • Minimize total track overflow under delay constraints

8. RTL Predictive PCM, Mutual Contraction, Wirelength Estimation Error Technology Mapping Placement Probabilistic CM (PCM) Routing Congestion Map (CM) Employing Placement-level Metric • Wirelength and mutual contraction cannot capture track overflow • Predictive probabilistic congestion map can • Same congestion map for different choices • Can we instead employ placement-/routing-level metric?

9. Pin 2 1 5/12 3/12 3/12 1/12 2 2/12 1/12 1/12 2/12 3 6 4 5 2/12 1/12 2/12 1/12 3/12 1/12 5/12 3/12 Pin 1 All routes equally possible: Probability of any route =1/6 Probabilistic Congestion Map • Probabilistic congestion map, a post-placement metric • Lou et al., TCAD’02; Westra et al., ISPD’04

10. RTL RTL Wire1 Technology Mapping Technology Mapping +Placement Wire2 Placement ? Probabilistic CM Probabilistic CM “Chicken-and-Egg” Problem • Overflow computation requires congestion map • Available after mapping • Track overflow of a wire depends on other cones also • Overflow due to Wire1depends on Wire2 and vice versa • Area or delay at Wire1do not depend on Wire2

11. Solution Overview • Track overflow cannot be computed incrementally, but congestion maps can. • Construct congestion maps using algebraic operations • Defer track overflow computation to covering • Requires congestion maps capturing all wires in mapping solutions • Overcome the “chicken-and-egg” problem: • Construct congestion maps bottom-up during matching • Compute track overflow during covering

12. Outline • Introduction • Algorithm Overview • Congestion Map Generation • Slack-constrained Covering • Results & Conclusion

13. M1 M3 M2 Cunknown The Matching Phase Delay M3 D2 M2 D1 M1 L1 L2 Load • Store the load-delay curve containing non-inferior delay matches • Performed for all nodes in topological order • Compute congestion map for each non-inferior match

14. 0.00 0.25 1.00 0.00 0.00 1.25 0.00 0.25 0.25 0.75 1.25 0.00 0.00 0.00 0.75 0.50 0.00 0.50 0.75 0.00 0.50 0.75 0.00 0.25 1.00 1.00 0.00 0.25 0.25 0.00 0.50 0.25 0.75 0.00 0.00 0.00 Algebraic Addition for Congestion Maps N2 N1 + M1 N3 + =

15. 0.8 0.4 0.2 0.1 0.4 0.2 N2 0.6 0.3 0.2 0.4 0.6 0.3 N1 0.2 0.4 0.2 0.1 0.2 0.1 N3 Handling Multiple Fanouts • For forward propagation, divide congestion maps by the number of fanouts • Allows correct computation of maps for solutions at PO’s

16. Congestion Map Generation • Congestion map for a match at a node represents wires from the fan-in cone only • Add congestion maps for matches at PO’s to get congestion map for an entire solution • Extensible to congestion based on fast global routing • Applicable to generation and propagation of any 2-D maps, e.g., power-density map

17. Outline • Introduction • Algorithm Overview • Congestion Map Generation • Slack-constrained Covering • Results & Conclusion

18. M1 M3 15 M2 Exploiting Slacks Delay • Classical covering: choose an optimum delay match • For Cload=15, M2 is optimal with Delay = 50 • Assume: slack of 10 • M1 and M3 also satisfy delay constraints • Allow non-delay-optimal matches on non-critical paths • M1 or M3 preferred if the corresponding overflows smaller 1 60 2 M3 40 M2 3 M1 10 10 20 Load

19. Slack-constrained Covering • Compute delays and slacks at the primary outputs (PO’s) due to delay-optimal solution • Compute corresponding congestion map • For all nodes in reverse topological order, • Compute delay and track overflow due to delay-optimal and congestion-optimal matches • If congestion-optimal match exists, store it • Else, store delay-optimal match • Propagate updated slacks to inputs of match

20. Extensions and Complexity • Slack-constrained covering applicable for • Different cost functions, e.g., maximum congestion • Traditional objectives, e.g., area, power • Time complexity • Linear in number of nodes (for a fixed library and layout area) • Run-times practical • Memory complexity • High memory requirement due to congestion map storage for all matches • Asymptotically same as conventional • Memory efficient variants possible • Current implementation applicable up to ~5,000 cells • Ideal for ECO mode hot-spot (re-)synthesis

21. Outline • Introduction • Algorithm Overview • Congestion Map Generation • Slack-constrained Covering • Results & Conclusion

22. Subject Graph Placement Technology Mapping Placement Routing Timing Analysis Experimental Setup • Mapping algorithm incorporated in SIS • Capo for placement • Timing driven routing • ISCAS’85 benchmarks • 100 nm process parameters from Predictive Technology Model • Library: enhanced lib2.genlib with up to 4 strengths for each gate • Experiments on 400 MHz Sun Ultra Sparc 60 • Comparison with conventional mapping in SIS

23. Track Overflow Comparison

24. Maximum Congestion Comparison

25. Delay Comparison

26. Row-utilization Comparison

27. Run-time Comparison

28. Summary of Experimental Results • Track overflows: 44% better • Delays: no adverse impact • Maximum congestion: 25% better • Row-utilization: no significant correlation • Run-times: 2x worse, but still practical

29. Conclusion • Presented a delay-optimal mapping algorithm to minimize routing congestion • Validated effectiveness on benchmark circuits • Algorithmic framework applicable for optimization of other cost functions and properties • Future directions • Implementation of memory efficient version • Placement-legalization based flow • Application to ECO-mode logic (re-)synthesis

30. Backup

31. Analogy with Classical Matching • Mapping for area optimization under delay constraint, Chaudhary et al., TCAD’95 • Similarities • The gate-area for a match at a given node represents gates only due to the nodes in the fan-in cone • Similarly, congestion map for a match at a given node represents wires due to the nodes in fan-in cone • Gate-area divided at multiple fanout points • Congestion-maps divided at multiple fanout points • Differences • Ensures delay optimality • Wire-delays accounted for in the delay computation • Routing congestion more complex than gate-area

32. Experimental Results

33. Experimental Results (Continued)