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Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Inverter. DIGITAL GATES Fundamental Parameters. Functionality Reliability, Robustness Area Performance DC Characteristics Speed (delay) Power Consumption.

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter

  2. DIGITAL GATES Fundamental Parameters • Functionality • Reliability, Robustness • Area • Performance • DC Characteristics • Speed (delay) • Power Consumption

  3. Noise in Digital Integrated Circuits

  4. The Ideal Gate

  5. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp)

  6. Mapping between analog and digital signals

  7. Definition of Noise Margins

  8. The Regenerative Property

  9. Fan-in and Fan-out

  10. V DD V V in out C L The CMOS Inverter: A First Glance

  11. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  12. VTC of Real Inverter

  13. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n V 0 V V = = in DD in (a) Low-to-high (b) High-to-low

  14. Delay Definitions

  15. Ring Oscillator

  16. Power Dissipation

  17. Voltage TransferCharacteristic

  18. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  19. DC Operation: Voltage Transfer Characteristic V(y) dVo/dVi =-1 V(x) V(y) V OH f V(y)=V(x) NML V Switching Logic Threshold LT NMH V OL VIL VIH V(x) V V OL OH Nominal Voltage Levels

  20. CMOS Inverter Load Characteristics I n,p V = 5 V = 0 in in NMOS PMOS V = 4 V = 4 V = 1 in in in V = 2 V = 3 V = 3 V = 2 in in in in V = 1 V = 4 in V = 2 V = 3 in in in V = 0 V = 5 in in Vout

  21. CMOS Inverter VTC • Vin < Vtn -NMOS Off • Vin > Vdd – Vtp -PMOS Off • PMOS: linear if Vsg –Vtp > Vsd • Vo > Vin +Vtp • NMOS: Linear if Vgs-Vtn > Vds • Vo < Vin –Vtn • VOH: PMOS(lin) & NMOS(off) • VOL: PMOS(off) & NMOS(lin) • VIH: PMOS(sat) & NMOS(lin) • VIL: PMOS(lin) & NMOS(sat) • VLT: PMOS(sat) & NMOS(sat)

  22. CMOS Inverter VTC VOH: PMOS(lin) & NMOS(off) = Vdd VOL: PMOS(off) & NMOS(lin) = Gnd VIH: PMOS(sat) & NMOS(lin): Solve: VIL: PMOS(lin) & NMOS(sat): Solve:

  23. CMOS Inverter VTC VLT: PMOS(sat) & NMOS(sat): If Vtn = Vtp & bp = bn  VLT = Vdd/2: Gives a symmetric Inverter!

  24. Simulated VTC

  25. 0.1 0.3 1.0 3.2 10.0 Gate Logic Switching Threshold 4.0 3.0 LT V 2.0 1.0 b /b p n

  26. Inverter Gain

  27. Gain=-1 Gain as a function of VDD

  28. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  29. Propagation Delay

  30. Delay Definitions

  31. CMOS Inverter: Transient Response

  32. CMOS Inverter Propagation Delay V DD t = C V /2 pHL L swing I av V out I C L av C L ~ k V V = V n DD in DD

  33. CMOS Inverter Propagation Delay V DD Vo VH NMOS(sat) Vdd Vdd-Vtn NMOS(lin) V out VL C L to t2 t1 Time V = V in DD

  34. CMOS Inverter Propagation Delay Similarly:

  35. CMOS Inverter Rise & Fall Time Similarly, Fall Time: Similarly, Rise Time:

  36. Computing the Capacitances

  37. The Miller Effect

  38. Computing the Capacitances

  39. Impact of Rise Time on Delay

  40. Delay as a function of VDD

  41. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn

  42. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  43. Design for Performance • Keep capacitances small • Increase transistor sizes • watch out for self-loading! • Increase VDD (????)

  44. Impact of Rise Time on Delay

  45. Inverter Sizing

  46. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

  47. Inverter Delay • Minimum length devices, L=0.7mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpHL = (ln 2) RNCL Delay (D): tpLH = (ln 2) RPCL Load for the next stage:

  48. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1

  49. Inverter with Load CP = 2Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

  50. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

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