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Lecture 5: DC & Transient Response

This lecture covers the DC and transient response in pass transistors, including logic levels, noise margins, RC delay models, and delay estimation. It discusses the operation of nMOS and pMOS pass transistors, load line analysis, and the impact of process variations. The lecture also explains delay definitions and estimation approaches for pass transistor circuits.

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Lecture 5: DC & Transient Response

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  1. Lecture 5: DC & Transient Response

  2. Outline • Pass Transistors • DC Response • Logic Levels and Noise Margins • Transient Response • RC Delay Models • Delay Estimation 5: DC and Transient Response

  3. Pass Transistors • We have assumed source is grounded • What if source > 0? • e.g. pass transistor passing VDD • Vg = VDD • If Vs > VDD-Vt, Vgs < Vt • Hence transistor would turn itself off • nMOS pass transistors pull no higher than VDD-Vtn • Called a degraded “1” • Approach degraded value slowly (low Ids) • pMOS pass transistors pull no lower than Vtp • Transmission gates are needed to pass both 0 and 1 5: DC and Transient Response

  4. Pass Transistor Ckts 5: DC and Transient Response

  5. DC Response • DC Response: Vout vs. Vin for a gate • Ex: Inverter • When Vin = 0 -> Vout = VDD • When Vin = VDD -> Vout = 0 • In between, Vout depends on transistor size and current • By KCL, must settle such that Idsn = |Idsp| • We could solve equations • But graphical solution gives more insight 5: DC and Transient Response

  6. Transistor Operation • Current depends on region of transistor behavior • For what Vin and Vout are nMOS and pMOS in • Cutoff? • Linear? • Saturation? 5: DC and Transient Response

  7. nMOS Operation Vgsn = Vin Vdsn = Vout 5: DC and Transient Response

  8. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 5: DC and Transient Response

  9. I-V Characteristics • Make pMOS is wider than nMOS such that bn = bp 5: DC and Transient Response

  10. Current vs. Vout, Vin 5: DC and Transient Response

  11. Load Line Analysis • For a given Vin: • Plot Idsn, Idsp vs. Vout • Vout must be where |currents| are equal in 5: DC and Transient Response

  12. Load Line Analysis • Vin = 0 • Vin = 0 0.2VDD 0.4VDD 0.6VDD 0.8VDD VDD 5: DC and Transient Response

  13. DC Transfer Curve • Transcribe points onto Vin vs. Vout plot 5: DC and Transient Response

  14. Operating Regions • Revisit transistor operating regions 5: DC and Transient Response

  15. Beta Ratio • If bp / bn 1, switching point will move from VDD/2 • Called skewed gate • Other gates: collapse into equivalent inverter 5: DC and Transient Response

  16. 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Switching Threshold 5: DC and Transient Response

  17. Inverter Gain

  18. Gain=-1 Gain as a function of VDD

  19. Simulated VTC

  20. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  21. Noise Margins • How much noise can a gate input see before it does not recognize the input? 5: DC and Transient Response

  22. Logic Levels • To maximize noise margins, select logic levels at • unity gain point of DC transfer characteristic 5: DC and Transient Response

  23. Transient Response • DC analysis tells us Vout if Vin is constant • Transient analysis tells us Vout(t) if Vin(t) changes • Requires solving differential equations • Input is usually considered to be a step or ramp • From 0 to VDD or vice versa 5: DC and Transient Response

  24. Inverter Step Response • Ex: find step response of inverter driving load cap 5: DC and Transient Response

  25. Delay Definitions • tpdr: rising propagation delay • From input to rising output crossing VDD/2 • tpdf: falling propagation delay • From input to falling output crossing VDD/2 • tpd: average propagation delay • tpd = (tpdr + tpdf)/2 • tr: rise time • From output crossing 0.2 VDD to 0.8 VDD • tf: fall time • From output crossing 0.8 VDD to 0.2 VDD 5: DC and Transient Response

  26. Delay Definitions • tcdr: rising contamination delay • From input to rising output crossing VDD/2 • tcdf: falling contamination delay • From input to falling output crossing VDD/2 • tcd: average contamination delay • tpd = (tcdr + tcdf)/2 5: DC and Transient Response

  27. Simulated Inverter Delay • Solving differential equations by hand is too hard • SPICE simulator solves the equations numerically • Uses more accurate I-V models too! • But simulations take time to write, may hide insight 5: DC and Transient Response

  28. Delay Estimation Approach 1

  29. Delay Estimation Approach 2 • We would like to be able to easily estimate delay • Not as accurate as simulation • But easier to ask “What if?” • The step response usually looks like a 1st order RC response with a decaying exponential. • Use RC delay models to estimate delay • C = total capacitance on output node • Use effective resistance R • So that tpd = RC • Characterize transistors by finding their effective R • Depends on average current as gate switches 5: DC and Transient Response

  30. Effective Resistance • Shockley models have limited value • Not accurate enough for modern transistors • Too complicated for much hand analysis • Simplification: treat transistor as resistor • Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R • R averaged across switching of digital gate • Too inaccurate to predict current at any given time • But good enough to predict RC delay 5: DC and Transient Response

  31. Delay Estimation Approach 2

  32. RC Delay Model • Use equivalent circuits for MOS transistors • Ideal switch + capacitance and ON resistance • Unit nMOS has resistance R, capacitance C • Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width 5: DC and Transient Response

  33. RC Values • Capacitance • C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm • Gradually decline to 1 fF/mm in nanometer techs. • Resistance • R  6 KW*mm in 0.6 mm process • Improves with shorter channel lengths • Unit transistors • May refer to minimum contacted device (4/2 l) • Or maybe 1 mm wide device • Doesn’t matter as long as you are consistent 5: DC and Transient Response

  34. Computing Capacitance • For an inverter driving an identical inverter, the capacitances in the intermediate node are: • Cgd12: Since the circuit input is digital, M1 and M2 are either in cut-off or active. Hence, Cgd12 are only overlap capacitances. • Cdb1 and Cdb2: These are the diffusion capacitances. They are voltage variable. Hence use the approximation Ceq = KeqCj0. • Cw: Wiring capacitance. • Cg3 and Cg4: Fanout capacitances 5: DC and Transient Response

  35. Computing Capacitance • Cgd12 is connected between input and intermediate node. • Use Miller approximation. • Use a large signal gain of -1. • Therefore, the approximate capacitance is given by 2Cov. • The wiring capacitance will be studied later. • The gate capacitance is given by: 5: DC and Transient Response

  36. Computing Capacitance • Actually, there are a few errors in the Cfanout calculation. • Miller effect is ignored here. • Not too bad because Vout of second gate does not change too much while the calculation is being done. • Channel capacitance is assumed to be constant. • It varies between (2/3)WLCox and WLCox. • The total error observed is about 10%. 5: DC and Transient Response

  37. Computing Capacitance 5: DC and Transient Response

  38. Delay Estimation • Let us use approach 1 first. • For approximate results, use the initial value of I 5: DC and Transient Response

  39. Delay Estimation • Then I is given by • Note that this is the long channel expression. You can use the velocity saturation or alpha power law expressions as well. 5: DC and Transient Response

  40. Delay Estimation • The propagation delay is then, 5: DC and Transient Response

  41. Delay Estimation • Let us use Approach 2. 5: DC and Transient Response

  42. Delay Estimation • Ignore l for simpler expressions 5: DC and Transient Response

  43. Delay Estimation • Keep C small • Increase transistor sizes • Is there a limit? • Increase supply voltage • Does this really work? 5: DC and Transient Response

  44. Delay as a function of VDD

  45. Delay Estimation • Assume a symmetrical inverter (tpLH = tpHL). • Break up CL into Cint and Cext • CL = Cint + Cext • Cint due to driving inverter itself (Cdiff, Cgd) • Cext due to outside (CL, Cw) • Then, delay can be written as • tp0 is intrinsic delay, self delay, unloaded delay. 5: DC and Transient Response

  46. Delay Estimation • Let us make the W of the transistors in the driving gate S times bigger to decrease delay. • tp0 is independent of the sizing of the gate and determined purely by technology and inverter layout. • Making S infinity gives the minimum delay, but after a certain point, the improvement is marginal. 5: DC and Transient Response

  47. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  48. Device Sizing • So far, we have tried to make tpHL = tpLH. • Is this optimum? 5: DC and Transient Response

  49. Device Sizing • Let us define the ratio of the ‘strengths’ of the PMOS and the NMOS as • Then, b can be obtained by finding the derivative of delay with respect to b. 5: DC and Transient Response

  50. NMOS/PMOS ratio tpLH tpHL b = Wp/Wn tp

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