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UWB4SN: Workshop on UWB for Sensor Networks Lausanne, 2005, Nov 4th. Energy Detection UWB Receiver Design using a Multi-resolution VHDL-AMS Description. Mario Casu, Mariagrazia Graziano VLSI Lab - Dip. Elettronica POLITECNICO DI TORINO. Outline. Why Energy Detection Receiver?

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energy detection uwb receiver design using a multi resolution vhdl ams description

UWB4SN: Workshop on UWB for Sensor Networks

Lausanne, 2005, Nov 4th

Energy Detection UWB Receiver Design using a Multi-resolution VHDL-AMS Description

Mario Casu, Mariagrazia Graziano

VLSI Lab - Dip. Elettronica

POLITECNICO DI TORINO

Lausanne 11/4/05, UWB4SN

outline
Outline
  • Why Energy Detection Receiver?
  • Why should I use VHDL-AMS?
  • How does the receiver work?
  • How do I simulate it?
  • Some answers…
  • Ongoing work
  • Conclusions

Lausanne 11/4/05, UWB4SN

why ed receiver
Why ED Receiver?
  • Applications: WPAN with localization capabilities, low power constraints, moderate (low) data-rate
    • Match IEEE 802.15.4a objectives
  • UWB impulse based enabling technology
  • Coherent receivers aren’t low power nor low complexity
    • indoor multipath ~100 replicas = ~100 Rake fingers?
    • need Nyquist sampling… ~10 GHz low power?
    • …or need analog template (impulse response) = simple?
  • Energy Detection is (relatively) simple
    • Square, Integrate & Dump, Sample (at pulse repetition rate!)
    • Trade performance with simplicity
  • GOAL: CMOS technology fully integrated ED receiver

Lausanne 11/4/05, UWB4SN

energy detection example

2 PPM modulation, including white noise and multipath

0

0

1

0

1

( · ) 2 and integrate in proper windows

0

0

1

0

1

10.3

3.4

9.7

3.4

3.4

10.5

6.8

3.4

3.4

9.1

0

1

0

1

0

1

0

1

0

1

max

max

max

max

max

0

1

0

0

1

Energy Detection: example

Lausanne 11/4/05, UWB4SN

transceiver architecture

RECEIVER BLOCKS

RF

Analog

Mixed

Digital

LNA

Transceiver architecture

MAC

PROC

Pulse Gen

Mod &

Coding

Channel

Coding

BP

Filter

( )2

dt & H

N-bit ADC

Demod &

Decoding

CCA

SYNCH

RANGING

Power

Management

Unit

CTRL

Lausanne 11/4/05, UWB4SN

why vhdl ams
Why VHDL-AMS?
  • The receiver contains RF, analog, digital and mixed blocks
  • A powerful co-simulation environment (e.g. ADMS™) enables simultaneous simulation of
    • VHDL (digital)
    • VHDL-AMS (analog/mixed)
    • Spice (circuit level)
  • Approach followed in this work:
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models

Lausanne 11/4/05, UWB4SN

example lna

RECEIVER BLOCKS

RF

Analog

Mixed

Digital

LNA

Example: LNA

entity LNA is

port (

terminal input, output: electrical);

end LNA;

architecture behavioral of LNA is

begin

end behavioral;

MAC

PROC

Pulse Gen

Mod &

Coding

Channel

Coding

BP

Filter

( )2

dt & H

N-bit ADC

Demod &

Decoding

CCA

SYNCH

RANGING

Power

Management

Unit

CTRL

Lausanne 11/4/05, UWB4SN

example lna1

RECEIVER BLOCKS

RF

Analog

Mixed

Digital

LNA

Example: LNA

entity LNA is

port (

terminal input, output: electrical);

end LNA;

architecture behavioral of LNA is

quantity vin across input to electrical_ref;

quantity vout across iout through output to electrical_ref;

begin

vout == vin * gain;

end behavioral;

MAC

PROC

Pulse Gen

Mod &

Coding

Channel

Coding

BP

Filter

( )2

dt & H

N-bit ADC

Demod &

Decoding

CCA

SYNCH

RANGING

Power

Management

Unit

CTRL

Lausanne 11/4/05, UWB4SN

example lna2

RECEIVER BLOCKS

RF

Analog

Mixed

Digital

LNA

Example: LNA

entity LNA is

port (

terminal input, output: electrical);

end LNA;

architecture behavioral of LNA is

quantity vin across input to electrical_ref;

quantity vout across iout through output to electrical_ref;

begin

if (abs(vin'Ltf(num,den)*gain+vos) < vsat) use

vout == vin'Ltf(num,den)*gain+vos;

else-- saturation

vout == vsat *sign(abs(vin'Ltf(num,den)*gain+vos);

enduse;

end behavioral;

MAC

PROC

Pulse Gen

Mod &

Coding

Channel

Coding

BP

Filter

( )2

dt & H

N-bit ADC

Demod &

Decoding

CCA

SYNCH

RANGING

Power

Management

Unit

CTRL

Lausanne 11/4/05, UWB4SN

matlab vs vhdl ams

No loss in accuracy

CPU Time:

MATLAB 1

VHDL-AMS-1 16.2

VHDL-AMS-2 1.53

Matlab vs VHDL-AMS

Simple 2-PPM with Channel Model IEEE 802.15.3a

Matlab

VHDL-AMS-1

continuous-time

VHDL-AMS-2

discrete-time

Lausanne 11/4/05, UWB4SN

how does the receiver work
How does the receiver work?
  • Listen to channel, measure noise energy (in Tbit) and set noise threshold Nth
  • If channel energy (in Tbit) < Nth then goto 1, else
    • Adjust gain
    • Coarse synchronization
    • Concurrent demodulation and fine synch
    • If Two-Way-Ranging (TWR) command, prepare for packet reply
    • Send coarse & fine synch info in replied packet payload

Lausanne 11/4/05, UWB4SN

clear channel assessment

LNA

Clear Channel Assessment

( )2

dt & H

N-bit ADC

Demod &

Decoding

input

CCA

CTRL

SYNCH

RANGING

Lausanne 11/4/05, UWB4SN

noise estimation

Integrate CK from Synch

strobe from CTRL

Noise Integrated and Dumped

ADC output

NOISY (INPUT)2

Noise Estimation

Lausanne 11/4/05, UWB4SN

preamble detection

strobe from CTRL

ADC output

Integrate CK from Synch

Non-modulated (INPUT)2

(INPUT)2 integrated and dumped

Preamble Detection

Lausanne 11/4/05, UWB4SN

gain adjustment

0111

1111

LUT

gain 0

gain 1

DAC

gain 7

gain 15

LNA

VGA

Gain Adjustment

( )2

dt & H

4-bit ADC

Demod &

Decoding

CCA

gain 7

SYNCH

RANGING

CTRL

Lausanne 11/4/05, UWB4SN

synchronization

data

coarse

Locked!

fine

Synchronization
  • ~ IEEE 802.15.4 packet
  • Simple 2 PPM : 1 pulse/symbol
  • Non modulated preamble is used for coarse synchronization
  • Must finish before Start of Frame Delimiter (SFD)
  • When locked, Fine Synchronization starts
  • Extends over non modulated pulses

4 bytes

1

1

variable length

preamble

SFD

payload

FL

Lausanne 11/4/05, UWB4SN

synchronization of 2 ppm signal

Non-modulated preamble: ( · ) 2 and integrate with a sliding window

10.5

6.0

3.4

9.7

6.8

4.5

t0+dt

t0

t0+2dt

t0+3dt

t0+4dt

t0+5dt

max

SYNCH TIME: t0+2dt

Synchronization of 2-PPM signal

0

0

0

0

0

0

Fine synch similar with finer increment step around coarse lock point

Lausanne 11/4/05, UWB4SN

coarse synch simulation

ADC output

Incremental delay

System CK

Integrate Strobe

Coarse Synch simulation

Lausanne 11/4/05, UWB4SN

demodulation

0

1

1

0

1

1

1

0

0

1

0

0

0

0

1

0

Start of Frame Delimiter

Frame Length = 10 Bytes

0

1

1

0

1

1

1

0

0

1

0

0

0

0

1

0

Demodulation

Lausanne 11/4/05, UWB4SN

putting it all together

Gain Set

Synch Search

Putting it all together

(INPUT)2

(Noise)2

SFD

Preamble Detect

Noise Estimate

Lausanne 11/4/05, UWB4SN

lessons learned
Lessons learned
  • Ideal simulations show system functionality
  • Problems arise when simulating effects like saturation and limited A/D resolution
  • Need for a reliable AGC. Example:
    • Given pulse energy and A/D N-bit, gain too low leads to bad synch (impossible to resolve integrated signal)
    • Gain too high leads to saturation: Same problem!
  • Ranging requisites stricter in terms of A/D resolution
    • OK 4 bits for coarse synch & demod
    • 1 more bit for fine synch and thus ranging

Lausanne 11/4/05, UWB4SN

ongoing work

~1ns

Ongoing Work
  • Transmitter design
    • Almost digital operation
    • Found sequence of pulses that best matches FCC/ETSI mask
  • Two Way Ranging Simulation
    • Old 802.15.3a CM used
    • Preliminary results show ~ns accuracy

Lausanne 11/4/05, UWB4SN

conclusions
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models

Lausanne 11/4/05, UWB4SN

conclusions1
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models

Lausanne 11/4/05, UWB4SN

conclusions2
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models

Lausanne 11/4/05, UWB4SN

conclusions3
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models

Lausanne 11/4/05, UWB4SN

conclusions4
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models
  • So far, VHDL-AMS proved to be effective in managing the design complexity at system simulation stage

Lausanne 11/4/05, UWB4SN

conclusions5
Conclusions
  • Status of the work
    • Build a behavioral system using VHDL and VHDL-AMS
    • Check consistency w. higher level simulation (Matlab)
    • Refine the description using more accurate models
    • Substitute analog and mixed blocks with Spice transistor-level models
  • So far, VHDL-AMS proved to be effective in managing the design complexity at system simulation stage
  • Next: Tracking IEEE 802.15.4a PHY

Lausanne 11/4/05, UWB4SN

slide29

That’s all Folks…

THANK YOU!

Lausanne 11/4/05, UWB4SN