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Minimum Systems and the PIC 16F84A. Chapter Two. Outline. Review of Memory Technologies The PIC 16 Series PIC 16F84A The PIC 16F84A Memory The Oscillator Instruction Cycle Power-up and Reset. Review of Memory Technologies. Read Only Memory (ROM) Random Access Memory (RAM): Read/Write

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minimum systems and the pic 16f84a

Minimum Systems and the PIC 16F84A

Chapter Two

Dr. Gheith Abandah

outline
Outline
  • Review of Memory Technologies
  • The PIC 16 Series
  • PIC 16F84A
  • The PIC 16F84A Memory
  • The Oscillator
  • Instruction Cycle
  • Power-up and Reset

Dr. Gheith Abandah

review of memory technologies
Review of Memory Technologies
  • Read Only Memory (ROM)
  • Random Access Memory (RAM): Read/Write
  • Static RAM (SRAM): Each cell is a simple flip-flop of six transistors, CMOS, volatile
  • Programmable ROM (PROM): Each cell is one transistor, MOS, non-volatile, plastic package.
  • Erasable PROM (EPROM): Each cell is one transistor, MOS, non-volatile, erasable with ultraviolet light, ceramic package with quartz window.

Dr. Gheith Abandah

review of memory technologies cont
Review of Memory Technologies – cont.
  • Electrically EPROM (EEPROM): Each cell is one transistor with additional transistors for programming, MOS, non-volatile, erasable electrically (takes time), suffers from wear.
  • Flash Memory: Each cell is one transistor, MOS, non-volatile, erasable electrically (takes time) in blocks, suffers from wear, popular.

Dr. Gheith Abandah

the pic 16 series
The PIC 16 Series

Dr. Gheith Abandah

the pic 16 series1
The PIC 16 Series

Dr. Gheith Abandah

the pic 16 series2
The PIC 16 Series

Dr. Gheith Abandah

pic 16f84a
PIC 16F84A

Dr. Gheith Abandah

pic 16f84a architecture
PIC 16F84A Architecture

Dr. Gheith Abandah

the 16f84a status register
The 16F84A Status Register
  • C: Carry/Borrow’
  • DC: Digit Carry/Borrow’
  • Z: Zero
  • PD’: Power Down
  • TO’: Time Out
  • RP0: Register Bank Select
  • RP1, IRP: Not implemented

Dr. Gheith Abandah

the 16f84a memory
The 16F84A Memory

Dr. Gheith Abandah

program memory and stack
Program Memory and Stack

Dr. Gheith Abandah

configuration word
Configuration Word

Allows the user to define certain configurable features of the microcontroller, at the time of program download.

Dr. Gheith Abandah

data memory and special function registers
Data memory and Special Function Registers

FSR: File Select Register for indirect addressing.

EEADR: EEPROM Address

EEDATA: EEPROM Data

EECON1: Control; RD, WREN, WR, EEIF

EECON2: 55H to AAH

Dr. Gheith Abandah

the oscillator
The Oscillator
  • It is necessary to provide the ‘clock’ signal.
  • The clock is a continuously running fixed frequency logic square wave.
  • The overall speed of the microcontroller operation is entirely dependent on this clock frequency.
  • Higher frequency -> Higher Performance and higher power consumption.

Dr. Gheith Abandah

instruction cycle
Instruction Cycle
  • The main oscillator signal is divided by 4 to produce the instruction cycle time.

Dr. Gheith Abandah

pipelining
Pipelining
  • All PIC microcontrollers implement pipelining.
  • Pipelining fails when one instruction changes the contents of the Program Counter.

Dr. Gheith Abandah

power up and reset
Power-up and Reset
  • At power-up, the Program Counter is forced to zero and the SFRs are reset so that peripherals are initially in a safe and disabled state.
  • There is also a master clear input MCLR’.

Dr. Gheith Abandah

summary
Summary
  • The PIC 16 Series is a diverse and effective family of microcontrollers.
  • The 16F84A architecture is representative of all 16 Series microcontrollers, with Harvard structure, pipelining and a RISC instruction set.
  • The PIC 16F84A has a limited set of peripherals, chosen for small and low-cost applications. It is thus a smaller member of the family, with features that are a subset of any of the larger ones.
  • The 16F84A uses three distinct memory technologies for its different memory areas.
  • A particular type of memory location is the Special Function Register, which acts as the link between the CPU and the peripherals.
  • Reset mechanisms ensure that the CPU starts running when the appropriate operating conditions have been met, and can be used to restart the CPU in case of program failure.

Dr. Gheith Abandah