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憶聲電子技術研討會. ACV 開發處 彭福醮 MAY, 14, 2004. AU180 Introduce. AU180 Price AU180 Chip architecture AU180 Firmware design guide AU180 to support panel. 1.AU180 Price. 2. Chip architecture. AU180 Block diagram. 2.0 Host interface.
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憶聲電子技術研討會 • ACV 開發處 彭福醮 • MAY, 14, 2004
AU180 Introduce • AU180 Price • AU180 Chip architecture • AU180 Firmware design guide • AU180 to support panel
2. Chip architecture • AU180 Block diagram
2.0 Host interface • User can configure AU180 via SPI interface. About read/write protocol of SPI interface.
2.1 Input Format Process • Auto phase (13H, 24H-27H): • Using to choose the right phase of ADC to sample the analog signal in graphic mode. • Auto position (13H, 14H-1BH): • Using to correct the position of input image in graphic mode. • Mode detection (13H, 1CH-23H): • Using to detect input format in both graphic & video input signal. Thus we can set related parameter of scaler to display image on the panel.
2.2 Scaling Engine • Using to scaling up input image to output panel
2.3 Brightness / Contrast Adjust • Rout = (Rin * Rcontrast) + Rbrightness • Gout = (Gin * Gcontrast) + Gbrightness • Bout = (Bin * Bcontrast) + Bbrightness
2.4 Internal OSD • The internal OSD block of AU180 is font based OSD. It can display total 640(32x20) fonts on screen and each of fonts composed by 8x16 pixels. The build in SRAM can store total 256 fonts and font size can zoom from default size.
2.5 OSD Mixer • OSD mixer can blending and transparency either internal or external OSD to input image.
2.6 Gamma & Dithering • GAMMA • The gamma table is used to adjust the RGB data for the display characteristics of the TFT panel. The lookup table has an 8-bit input(256 different RGB entries) and produces a 10-bit output. • Dithering • For TFT panel that have fewer than eight bits for each R, G, B input, the AU180 provides ordered and random dithering patterns to help smoothly shade colors on 6-bit • .
2.8 Build-in Display PLL • AU180 has build-in PLL to generate clock for all function blocks. It provides a wide range of user-programmable frequency synthesis options, and the formula as following: • Dclk = Fin * M / N / P
2.9 PWM • AU180 has 2 channels 8 bits PWM output. It normally use to provide inverter brightness and audio volume control.
3. Firmware design guide • Firmware flow chart
3.2 Get Remote Key • We use Timer 0 and Interrupt 0 to process remote control signal. Following are some brief rule of remote state machine • If customer and data code are correct then push data code to key buffer. • If repeat code is received and repeat debounce is timeout then push the same data code to key buffer. • If time duration of any state is miss match then RC state machine will back to start point.
3.3 Get Keypad Key • Keypad process is similar to remote control. We use 32 ms time tick to check key scan process in main routine. Following are some brief rule of key scan state machine • If key is pressed and key press debounce is timeout then push key to key buffer. • If key is still press down and key repeat debounce is timeout then push key to key buffer. • If key is released then back to key scan state machine start point.
3.4 OSD Handler • OSD handler is use to process key event and display corresponding OSD message. Following are some brief rule of key scan state machine • Get key code from key buffer • According key code to execute related function • Display OSD message • Store changed variable to EEPROM
3.5 Mode Detection • Mode detection procedure is use to detect current video mode status, and control related device when video mode is changed.
