Elec 7770 advanced vlsi design spring 2008 retiming
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ELEC 7770 Advanced VLSI Design Spring 2008 Retiming. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html. Retiming.

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Elec 7770 advanced vlsi design spring 2008 retiming

ELEC 7770Advanced VLSI DesignSpring 2008Retiming

Vishwani D. Agrawal

James J. Danaher Professor

ECE Department, Auburn University

Auburn, AL 36849

vagrawal@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html

ELEC 7770: Advanced VLSI Design (Agrawal)


Retiming
Retiming

  • Retiming is a function-preserving transformation of a synchronous sequential circuit.

  • Flip-flops are moved according to specific rules.

  • Original references:

    • C. E. Leiserson, F. Rose and J. B. Saxe, “Optimizing Synchronous Circuits by Retiming,” Proc. 3rd Caltech Conf. on VLSI, 1983, pp. 87-116.

    • C. E. Leiserson and J. B. Saxe, “Retiming Synchronous Circuitry,” Algorithmica, vol. 6, pp. 5-35, 1991.

ELEC 7770: Advanced VLSI Design (Agrawal)


A trivial example reduced hardware
A Trivial Example: Reduced Hardware

FF

FF

FF

ELEC 7770: Advanced VLSI Design (Agrawal)


Example 2 faster clock
Example 2: Faster Clock

FF

FF

ELEC 7770: Advanced VLSI Design (Agrawal)


Example 3 reduced flip flops
Example 3: Reduced Flip-Flops

FF

FF

FF

ELEC 7770: Advanced VLSI Design (Agrawal)


Applications of retiming
Applications of Retiming

  • Performance optimization

  • Area optimization

  • Power optimization

  • Testability enhancement

  • FPGA optimization

ELEC 7770: Advanced VLSI Design (Agrawal)


Fundamental operation of retiming
Fundamental Operation of Retiming

  • A retiming move in a circuit is caused by moving all of the memory elements at the input of a combinational block to all of its outputs, or vice-versa.

FF

Combinational

logic

Combinational

logic

FF

FF

ELEC 7770: Advanced VLSI Design (Agrawal)


A correlator circuit
A Correlator Circuit

Adder

delay = 7

+

+

+

PO

host

PI

=

=

=

=

a1

a2

a3

a4

Comparator

delay = 3

Flip-flop

ELEC 7770: Advanced VLSI Design (Agrawal)


Graph model
Graph Model

f

e

g

0

0

7

7

7

0

0

0

0

0

0

h

1

3

3

3

3

1

1

1

a

b

c

d

Vertex, vi, combinational, delay = d(vi), assumed unchanged by retiming

d(host) = 0

Edge, e(vi,vj) or eij, weight wij = number of flip-flops between vi and vj

ELEC 7770: Advanced VLSI Design (Agrawal)


Path delay and path weight
Path Delay and Path Weight

  • A set of connected nodes specify a path. A path does not traverse through the host node.

  • Path delay = ∑ d(vi) = combinational delay of path

  • Path weight = ∑ wij = clock delay of path

  • Retiming of a node i is denoted by an integer ri

    • It represents the number of registers moved across, initially ri = 0

    • Register moved from output to input, ri → ri + 1

    • Register moved from input to output, ri → ri – 1

    • After retiming, edge weight wij’ = wij + rj – ri

ELEC 7770: Advanced VLSI Design (Agrawal)


Example of node retiming
Example of Node Retiming

r1 = 0 r2 = 0 r3 = 0 r4 = 0 r5 = 0 r6 =0

3

3

3

3

3

3

∑ d(vi) = 12, ∑ wij = 0

r1 = 0 r2 = -1 r3 = 0 r4 = 0 r5 = 1 r6 =0

3

3

3

3

3

3

∑ d(vi) = 12, ∑ wij = 2

ELEC 7770: Advanced VLSI Design (Agrawal)


Legal retiming
Legal Retiming

  • Retiming is legal if the retimed circuit has no negative weights.

  • A legally retimed circuit is functionally equivalent to the original circuit – proof by Leiserson and Saxe (1991)

  • Retiming is the most general method for changing the register count and position without knowing the functions of vertices.

ELEC 7770: Advanced VLSI Design (Agrawal)


Example
Example

FF

a

c

b

x

d

c

1

0

x

host

0

0

ELEC 7770: Advanced VLSI Design (Agrawal)


Example illegal retiming
Example: Illegal Retiming

0

0

c

1

c

1 → 0

0

0

x

x

host

host

0

0 → –1

0

0 → –1

0

0

0

0 →1

Retiming vector = {0, 0, 0}

Retiming vector = {0, 0, –1}

a

c

FF

x

b

d

ELEC 7770: Advanced VLSI Design (Agrawal)


Example legal retiming
Example: Legal Retiming

0 →1

0

1 → 0

c

1

c

0

0 →1

x

x

host

host

0

0

0

0

0

0

0

0

Retiming vector = {0, 1, 0}

Retiming vector = {0, 0, 0}

FF

a

c

FF

b

x

d

ELEC 7770: Advanced VLSI Design (Agrawal)


Correlator circuit
Correlator Circuit

Critical path delay = 24

f

g

e

0

0

7

7

7

re=0

0

rf=0

rg=0

0

0

0

0

0

h

rh=0

1

3

3

3

3

1

1

1

rd=0

rb=0

rc=0

ra=0

a

c

b

d

Initial retiming vector = {0,0,0,0,0,0,0,0}

ELEC 7770: Advanced VLSI Design (Agrawal)


Retimed correlator circuit
Retimed Correlator Circuit

Critical path delay = 13

f

g

e

0→1

0→1

7

7

7

re= -2

0

rf= -1

rg=0

0

0

0

0→1

0

h

rh=0

1→0

1→0

1

3

3

3

3

1

rd= -2

rb= -1

rc= -2

ra= -1

a

c

b

d

retiming vector = {-1,-1,-2,-2,-2,-1,0,0}

ELEC 7770: Advanced VLSI Design (Agrawal)


Retiming theorem
Retiming Theorem

  • Given a network G(V, E, W) and a cycle time T, (r1, . . . ) is a feasible retiming if and only if:

    • ri – rj ≤ wij for all edges (vi,vj) ε E

    • ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such that D(vi,vj) > T

      Where,

      W(vi,vj): is the minimum weight for all paths between vi and vj

      D(vi,vj): is the maximum delay among all minimum weight paths between vi and vj

ELEC 7770: Advanced VLSI Design (Agrawal)


Proof of condition 1
Proof of Condition 1

  • We assume that the original network is legal, i.e., all edge weights are positive.

  • For an arbitrary edge (vi,vj) ε E:

    ri – rj ≤ wij or wij + rj – ri ≥ 0, means that after retiming the new weight wij’ = wij + rj – ri will be positive. Thus, condition 1 ensures the legality of retiming.

ELEC 7770: Advanced VLSI Design (Agrawal)


Proof of condition 2
Proof of Condition 2

  • Given: d(vi) < T, for all i.

  • Any retimed path whose combinational delay exceeds clock period, will have at least one flip-flop.

  • The above is the requirement for correct operation.

rj flip-flops

ri flip-flops

Wij flip-flops

i

j

Path (i,j), D(i,j) > T

Original weight, Wij

Retimed weight, Wij’ = Wij + rj – ri ≥ 1

ELEC 7770: Advanced VLSI Design (Agrawal)


References
References

  • Two papers by Leiserson et al. (see slide 2).

  • G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.

  • N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Boston: Springer, 1999.

ELEC 7770: Advanced VLSI Design (Agrawal)