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FPGA System Design with Verilog. A Workshop Prepared for Rose-Hulman Ventures Ed Doering. Workshop Goals. Gain familiarity with FPGA devices Gain familiarity with HDL design methods Implement basic designs in hardware. Agenda. FPGA Overview. What is an FPGA?.

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FPGA System Design with Verilog


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    1. FPGA System Design withVerilog A Workshop Prepared for Rose-Hulman Ventures Ed Doering

    2. Workshop Goals • Gain familiarity with FPGA devices • Gain familiarity with HDL design methods • Implement basic designs in hardware FPGA System Design with Verilog

    3. Agenda FPGA System Design with Verilog

    4. FPGA Overview FPGA System Design with Verilog

    5. What is an FPGA? • Field Programmable Gate Array • Blank slate for your digital hardware system FPGA System Design with Verilog

    6. FPGA in Context • Microprocessor/microcontroller • Executes a program • Fixed hardware and interconnections • Full-custom IC • Design at the transistor level FPGA System Design with Verilog

    7. FPGA in Context • Semicustom IC • Standard cell (CBIC, ASIC) • Masked gate array (MGA) • Programmable logic device (PLD) • PLD • Complex PLD (CPLD) • FPGA FPGA System Design with Verilog

    8. When to Use an FPGA • Design economics • Shortest time to market • Lowest NRE cost • Highest unit cost • Make quick grab for market share, then do cost reduction with ASICs FPGA System Design with Verilog

    9. FPGA Pictures • Board • Packages • Wafer • Die photos • FPGA • Pentium II microprocessor Sources: http://www.xilinx.com/company/press/products/pictures2.htm, http://micro.magnet.fsu.edu/chipshots/pentium/ FPGA System Design with Verilog

    10. Internal Architecture • Array of Configurable Logic Blocks (CLBs) • User-defined (SRAM-based) interconnect between CLBs • Dedicated resources • Power distribution • Clock distribution • Programmable I/O blocks (IOBs) FPGA System Design with Verilog

    11. Configurable Logic Block Source: Smith, M.J.S., Application-Specific Integrated Circuits,Addison-Wesley, 1997. FPGA System Design with Verilog

    12. Programmable I/O Block Source: Smith, M.J.S., Application-Specific Integrated Circuits, ddison-Wesley, 1997. FPGA System Design with Verilog

    13. PLD Vendors Source: Xilinx University Program Workshop Notes FPGA System Design with Verilog

    14. Xilinx FPGA Product Families • Virtex-II (“Platform FPGA, ” 10M gates) • Virtex (1M gates), Virtex-E (3M gates) • Spartan (low cost ASIC replacement) • XC4000 (first FPGA family, now with enhancements) FPGA System Design with Verilog

    15. Altera FPGA Product Families • APEX-II (up to 7M gates) • APEX20K (up to 1.5M gates) • Mercury (ASIC replacement, “ASSP”) • FLEX 10K FPGA System Design with Verilog

    16. Hybrid FPGA / Microcontroller • Triscend E5 CSoC (configurable system-on-chip) • 8-bit 8051-based microcontroller • 40K system gates • Triscend A7 CSoC • 32-bit ARM7TDMI processor • 40K system gates FPGA System Design with Verilog

    17. Hybrid FPGA / Microcontroller • Atmel FPSLIC (Field Programmable System-Level Integrated Circuit) • 5K to 40K system FPGA gates • 8-bit AVR RISC microprocessor core • Microcontroller peripherals • 36K program and data RAM FPGA System Design with Verilog

    18. Choosing CPLD or FPGA • CPLD • Nonvolatile (ROM- or EEPROM-based) • Predictable delays (no routing) • “Register poor” (relatively few FFs) • Low-to-medium density • For simple, fast logic with many inputs • Specialized decoders, combinational circuits, counters FPGA System Design with Verilog

    19. Choosing CPLD or FPGA • FPGA • Volatile (SRAM-based) • Configuration must be stored externally (serial EEPROM) • Permits field upgrades, reconfigurable computing • Variable routing delays • “Register rich” (relatively many FFs) • For arbitrary digital systems, system-on-chip (SoC), medium-to-high density FPGA System Design with Verilog

    20. Verilog Overview FPGA System Design with Verilog

    21. Verilog Gateway Design Automation (1983; proprietary) Acquired by Cadence 1989 IEEE standard in 1995 Similar to C VHDL Origins in DoD VHSIC program (1980’s) IEEE standard in 1987 Similar to ADA Hardware Description Languages FPGA System Design with Verilog

    22. Verilog vs. VHDL • Verilog is less “wordy” • Industry is about 50%-50% • VHDL more common in adademe • I think Verilog is easier to learn FPGA System Design with Verilog

    23. What is “HDL”? • HDL = Hardware DescriptionLanguage • A text-based method for describing hardware to a synthesis tool FPGA System Design with Verilog

    24. HDL Advantages Over Schematic Entry • Produce correct designs in less time • Produce larger and more complex systems per unit time • Shifts focus to specifying functionality • Synthesis tools automate details of connecting gates and devices FPGA System Design with Verilog

    25. Design Flow Comparison Schematic Text Netlist HDL Sim Gate-Level Simulation HardwareSynthesis Implement Netlist Implement FPGA System Design with Verilog

    26. Key Advantages of HDL-Based Design Methodology • Operate at higher level of abstraction • Can debug earlier (behavioral simulator) • Parameterized design, easy to make wholesale modifications to a design (e.g., bus width) FPGA System Design with Verilog

    27. Key Advantages of HDL-Based Design Methodology • Can quickly specify desired behavior • Example: Up-counter with reset if (reset == 1) count <= 0; else count <= count + 1; FPGA System Design with Verilog

    28. Key Advantages of HDL-Based Design Methodology • Can easily target multiple devices (eases product migration) HDL FPGA ASIC FPGA System Design with Verilog

    29. Key Advantages of HDL-Based Design Methodology • HDL is more universal than schematic tools • Promotes design reuse • Promotes integration of third party designs, or IP (intellectual property) FPGA System Design with Verilog

    30. What HDL is NOT • HDL is not a programming language(HDL is a description language) • HDL is not highly abstract, e.g., implement the DSP algorithm y(n) = 0.75y(n-1) + 0.3x(n)(HDL is at the RTL level (register transfer)) FPGA System Design with Verilog

    31. Synthesizable Subset • Verilog (and VHDL) began life as simulation and modeling tools • Hardware synthesis developed during the 1990’s • Need to use a subset of Verilog and specific coding styles to allow synthesis tool to infer correct (and realizable) hardware FPGA System Design with Verilog

    32. Synthesizable Subset Use this to writetestbenches for behavioral simulation Verilog SynthesizableVerilog Use this to make hardwarein FPGA FPGA System Design with Verilog

    33. Most Likely Learning Hurdle • May try to write HDL code as if it will eventually be “executed” by some mysterious processor device in the FPGA • Code is written sequentially (like a program), but you are simply writing descriptions of the various hardware entities in your system FPGA System Design with Verilog

    34. Verilog: Combinational Circuits FPGA System Design with Verilog

    35. A Gradual Introduction • New concepts in boldface • Verilog keywords in italic • Refer to your handout... FPGA System Design with Verilog

    36. “Do Nothing” Circuit module Gadget; endmodule FPGA System Design with Verilog

    37. “Do Nothing” with I/O module Gadget (a,b,c);// Port modesinput a,b;output c; endmodule FPGA System Design with Verilog

    38. NAND Gate: Continuous Assignment module Gadget (a,b,c);/* Port modes */input a,b;output c;// Functionalityassign c = ~(a & b); endmodule FPGA System Design with Verilog

    39. Bitwise Operators ~ NOT & AND | OR ^ EXOR FPGA System Design with Verilog

    40. NAND Gate: Procedural Assignment module Gadget (a,b,c);// Port modesinput a,b;output c;// Registered identifiersreg c;// Functionalityalways @ (a or b) c <= ~(a & b); endmodule FPGA System Design with Verilog

    41. Two Gates module Gadget (a,b,c,d);// Port modesinput a,b;output c;output d;// Registered identifiersreg c,d;// Functionalityalways @ (a or b) begin c <= ~(a & b);d <= a ^ b;end endmodule FPGA System Design with Verilog

    42. Two-Input MUX moduleMux2 ( A, // A input B, // B input Sel, // Selector Y // Output);// Port modesinput A,B,Sel;output Y; // Registered identifiersreg Y;// Functionalityalways @ (A or B or Sel)if (Sel==0) Y <= A;else Y <= B; endmodule FPGA System Design with Verilog

    43. Relational Operators == Equal to!= Not equal< Less than> Greater than<= Less than or equal>= Greater than or equal&& AND|| OR FPGA System Design with Verilog

    44. More Operators >> Shift right<< Shift left+ Add- Subtract* Multiply/ Divide% Modulus Not likely to synthesize! FPGA System Design with Verilog

    45. MUX Again... // Functionalityalways @ (A or B or Sel)if(Sel) Y <= B;else Y <= A; FPGA System Design with Verilog

    46. ... and Again! // Functionalityalways @ (A or B or Sel) Y <= (Sel) ? B : A; FPGA System Design with Verilog

    47. 4-Input MUX module Mux4 ( Data, // Data input Sel, // Selector Y // Output);// Port modesinput [3:0] Data;input [1:0] Sel;output Y; // Registered identifiersreg Y;// Functionalityalways @ (Data or Sel)if (Sel == 0) Y <= Data[0];else if (Sel == 1) Y <= Data[1];else if (Sel == 2) Y <= Data[2];else Y <= Data[3];endmodule FPGA System Design with Verilog

    48. 4-Input MUX Using ‘case’ // Functionalityalways @ (Data or Sel)case (Sel)0: Y <= Data[0];1: Y <= Data[1];2: Y <= Data[2];3: Y <= Data[3];default: Y <= Data[0];endcase FPGA System Design with Verilog

    49. Custom MUX module Mux16 ( Data, // Data input Sel, // Selector Y // Output);// Port modesinput [15:0] Data;input [3:0] Sel;output Y; // Registered identifiersreg Y;// Functionalityalways @ (Data or Sel)casez (Sel)4’b0000: Y <= Data[0];4’b0001: Y <= Data[1]; 4’b01??: Y <= Data[2];default: Y <= Data[3];endcaseendmodule FPGA System Design with Verilog

    50. Code Translator (Truth Table) module Code_Translator ( Code_In, Code_Out, );// Port modesinput [2:0] Code_In;output [2:0] Code_Out;// Registered identifiersreg [2:0] Code_Out;// Functionalityalways @ (Code_In)case (Code_In) 3’b000: Code_Out <= 3’b101; 3’b001: Code_Out <= 3’b111; 3’b010: Code_Out <= 3’b001; 3’b011: Code_Out <= 3’b000; 3’b100: Code_Out <= 3’b100; 3’b101: Code_Out <= 3’b010; 3’b110: Code_Out <= 3’b110; 3’b111: Code_Out <= 3’b011;endcaseendmodule FPGA System Design with Verilog