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Computer Organization and Architecture William Stallings 8th Edition. Chapter 2 Computer Evolution and Performance. BRIEF HISTORY OF COMPUTERS The First Generation: Vacuum Tubes. ENIAC - background. Electronic Numerical Integrator And Computer

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computer organization and architecture william stallings 8th edition

Computer Organizationand Architecture William Stallings 8th Edition

Chapter 2Computer Evolution and Performance

eniac background
ENIAC - background
  • Electronic Numerical Integrator And Computer
  • Eckert and Mauchlyproposed to build a general-purpose computer using vacuum tubes for the BRL’s application.
  • At university of Pennsylvania
  • It was the world’s first general purpose electronic digital computer.
  • Started 1943
  • Finished 1946
    • Too late for war effort
  • Used until 1955
eniac details
ENIAC - details
  • The ENIAC was a decimal rather than a binary machine. Numbers were represented in decimal form, and arithmetic was performed in the decimal system.
  • Its memory consisted of 20 accumulators of 10 digits number.
  • It had to be programmed manually by setting switches and plugging and unplugging cables.
  • The resulting machine was enormous, weighing 30 tons, occupying 1500 square feet of floor space, and containing more than 18,000 vacuum tubes.
eniac details1
ENIAC - details
  • When operating, it consumed 140 kilowatts of power.
  • It was also substantially faster than any electromechanical computer, capable of 5000 additions per second.
von neumann turing
Von Neumann/Turing
  • The idea is a computer could get its instructions by reading them from memory, and a program could be set or altered by setting the values of a portion of memory.
  • This idea, known as the stored-program concept.
  • The first publication of the idea was in a 1945 proposal by von Neumann for a new computer, the EDVAC (Electronic Discrete Variable Computer).
von neumann turing1
Von Neumann/Turing
  • In 1946, von Neumann and his colleagues began the design of a new stored program computer, referred to as the IAS computer, at the Princeton Institute for Advanced Studies.
  • The general structure of the IAS computer consists of:
    • Main memory stores data and instructions1
    • Arithmetic and logic unit (ALU)capable of operating on binary data.
    • Control unit (CU) interprets instructions in memory to be executed.
    • Input and output (I/O) equipment operated by the control unit.
  • Completed 1952.
slide9

all of today’s computers have this same general structure and function and are thus referred to as von Neumann machines.

IAS Memory Formats:

  • The memory of the IAS consists of 1000 storage locations, called words, of 40 binary digits (bits) each.
  • Both data and instructions are stored there.
  • Numbers are represented in binary form, and each instruction is a binary code.
  • Each number is represented by a sign bit and a 39-bit value.
  • A word may also contain two 20-bit instructions, with each instruction consisting of an 8-bit operation code (opcode) specifying the operation to be performed and a 12-bit address designating one of the words in memory (numbered from 0 to 999).
structure of ias computer
Structure of IAS Computer
  • The control unit operates the IAS by fetching instructions from memory and executing them one at a time.
  • Both the control unit and the ALU contain storage locations, called registers, defined as follows:
      • Memory buffer register (MBR).
      • Memory address register (MAR).
      • Instruction register (IR).
      • Instruction buffer register (IBR).
      • Program counter (PC).
      • Accumulator (AC) and multiplier quotient (MQ)
slide12

Memory buffer register (MBR) contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.

  • Memory address register (MAR) specifies the address in memory of the word to be written from or read into the MBR.
  • Instruction register (IR) contains the 8-bit opcode instruction being executed.
  • Instruction buffer register (IBR) holds temporarily the right hand instruction from a word in memory.
slide13

Program counter (PC) contains the address of the next instruction-pair to be fetched from memory.

  • Accumulator (AC) and multiplier quotient (MQ) hold temporarily operands and results of ALU operations.
  • Next figure is to display the expanded structure of IAS Computer.
ias details
IAS - details
  • 1000 x 40 bit words
    • Binary number
    • 2 x 20 bit instructions
  • Set of registers (storage in CPU)
    • Memory Buffer Register
    • Memory Address Register
    • Instruction Register
    • Instruction Buffer Register
    • Program Counter
    • Accumulator
    • Multiplier Quotient