Abraham Gallas for the LHCb VELO Upgrade

1. The LHCb Upgrade from 1 to 40 MHz readout The 20th Anniversary International Workshop on Vertex Detectors 19-24 June 2011, Rust,Austria Abraham Gallas for the LHCb VELO Upgrade

2. Outline: • The LHCb upgrade: scenario & strategy • The Vertex detector upgrade: • Environment & plan • Detector module design & layout • Sensor options • ASIC design • Data readout rates • RF foil and material constraints • Cooling • Prototyping results from test beams • Summary

3. The LHCb upgrade • The Plan: • LHCb is currently running with excellent performance at higher luminosity than the nominal: L= 21032 cm–2s-1 • The experiment will collect ~ 5fb-1 before the 2nd LHC shutdown circa 2017  will largely cover the Physics goals of the experiment • During this shutdown we want to upgrade the detector to run at higher luminosity: L= 1033cm–2s-1 to collect 50 fb-1 (5fb-1/year) and increased energy √s = 14 TeV • This does not depend on any (HL)-LHC machine upgrade

4. The LHCb upgrade • Problem: The L0 hadron hardware trigger loses efficiency at higher luminosities: • Because the DAQ event readout rate is limited to 1MHz  trigger thresholds (ET) need to be raised… • Solution: • No hardware trigger, increase the readout rate to 40MHz and implement a fully software-based trigger in the CPU farm Current DAQ Upgraded DAQ LLT L0 Front-end Front-end L0-buffer 40MHz 1MHz Tell40 + LLT-buffer Tell1 5-10MHz 1MHz router router 5-10MHz 1MHz CPU-farm CPU-farm Max 3 kHz Max 20 kHz Storage Storage ~ 50 kB ~ 100 kB

5. Environment: radiation challenge The sensors edges placed at 7mm from the beam line during “stable beams”. After 50 fb-1 they see a fluence > 4x1015 1 MeV neq cm-2 Recent RD50 studies have shown that silicon irradiated at these levels still delivers a signal of ~ 10ke- / MIP Severe & non-uniform irradiation damage. Dose after 50 fb-1 185 MRad or 4.1 1015neq/cm2 7mm After that dose, we expect currents of ~120 mA/cm2 @ -15 °C and Vbias= 900 V  Danger of thermal runaway at the tip of the sensor from bulk current and heat injected by ROC • Efficient heat removal mandatory to avoid thermal runaway!! • Low noise electronics to cope with reduced signal

6. Environment: data rate challenge • Electronics has to digitize, zero suppress and transmit event data at 40 MHz • By pixel standards the occupancy of the VELO is miniscule, but the data rate is HUGE • 1 chip O(1cm2) has to transmit ~13 Gbit s-1 • Our current granularity, occupancies = ok but FE electronics and DAQ are not Particle occupancy per event (simulation) ~ 5 particles/cm2/event at r=7.0 mm Particle Hits / Event / cm2 radius (cm) Curves fitted to A.r-1.9

7. VELO Upgrade plan • Different systems of the current VELO1 will be retained: • CO2 cooling plant • LV & HV power supply systems • Vacuum vessel and equipment • Motion system • Major new components: • Detector modules based on pixel sensors • New readout ASIC: ´VELOPIX´ • Enhance module cooling interface • New design of low material RF foil between beam and detector vacua • Multi Gb s-1 readout system • Main design concerns: • Efficient cooling to avoid thermal runaway • Handle the huge data rate • Reduce material budget • Maintain if not improve the excellent performance2: • Proper time resolution ~ 50 fs • IP resolution ~ 13 + 25/pT μm Replace • 1,2See talk by Kazu AKIBA, SilviaBorghi

8. Velo Pixel module • Sensor tiles: 3 readout ASICs on a single sensor, with a guard ring ~500 μm • 2 sensor tiles are mounted on opposite sides of a substrate: • Readout & power traces on the substrate • Substrate choices: • CVD diamond: excellent mechanical &thermal properties: => low mass • Carbon fibre/TPG or Al/TPG • Material in sensitive region ~ 0.8%X0 • Prototype work started using Timepix ROCs (@ CNM). ~43mm ~15mm ASIC Sensor tile : sensor ASIC 60μm Kapon+120μm Al ASIC Cooling channel Substrate 400um Glue 50um Connector Top Sensor 200um ASIC150um Bot Sensor 200um ASIC150um

9. Pixel module & detector layout • A ‘station’ is made of 8 sensor tiles. • active area ~100% (except small gaps) • Closest pixel isat 7.5 mm from the beam center top tiles, bottom tiles ~ 1 mm gap BEAM • The full detector is composed of 26 stations • The modules on either side of the beam are staggered to create overlap regions • This layout has been simulated to be fully efficient (~98.3%, 4 hit per track) in the LHCb acceptance 15-250x300mrad beam Varying spacing along the beam axis. Minimal pitch 24 mm

10. Sensor options R&D • Planar Silicon: • Thin sensors seem well suited to the high fluences • R&D focus is on: • Reducing guard ring size. (closer approach to the beam, better impact parameter resolution) • More exotics solutions: trenches, laser scribing & Al2O3 Sidewall passivation (under investigation) • Reducing thickness. (less X0, lower bias voltage) • Several wafers with various manufacturers • CNM/USC : 150μm p-in-n sensors, 150-200μm n-in-p sensor single ASICs and later in the year 3x1 ASICs tiles • Micron/Liverpool: n-in-p (150 and 300μm thick) • VTT: slim edge (active) 50,100μmedge, different GR, 50-200 μm thick • Irradiation campaign up to 1.4 x 1016 MeV neq/cm2: • Planar silicon + Medipix3  check performance in test beam • Different GR structures to be fabricated at the manufacturers d Dicing distances= 250μm, 400μm, 600μm Distance calculated from the active area. One guard ring. CNM G. Pellegrini et al. Marc Christophersenet al.

11. Sensor options R&D • 3D sensors: • Lower depletion voltage and low power  less critical for thermal runaway • Greater signal charge due to faster collection time (less trapping)  potentially super radiation hard • Active edge allows closer approach to beam • Double-sided increase yield and improved areas of inefficiency • Many Medipix /Timepix assemblies available • Diamond p-CVD: • No thermal run away problem! • Very radiation hard • Double act: sensor and thermal path • Financially affordable for the VELO upgrade ( total surface ~ 1340 cm2 ) • Produced 1.43 x 1.43 cm2 , 750 mm thick sensor • Will produce Timepix assemblies for position resolution studies in testbeam Fluence (1015 1 MeV neq cm-2) 90Sr

12. Strip-based alternative design • Designed new R & F strip sensors, as ‘backup’ solution in case material budget or power of the pixel detector beyond acceptable levels: • 30 mm minimum pitch, 20 x 128 strips per sensor • Goal : keep occupancies < 0.6 % at 1033cm-2s-1 • Signal to Noise ratio after 50 fb-1: • Keep strip capacitance low • Remove pitch adapter to FE ROC • 40MHz rad-hard ROC to be designed: • Adapted to low capacitance detector • Programmable ZS data transmission • Possible synergy with ST upgrade • Sensitive area less than 500 mm from edge. First strip at 7.5 mm from beam • Reduce X0 • Test of prototypes from Hamamatsu this year Pixels Strips

13. ASIC development Timepix(now)  Timepix2(end 2011)  VELOPIX(2012) • 256x256 pixels, size (55mm x 55 mm) gives equal spatial precision in both directions, removing the need for double sided modules (factor 2 in material) • IBM 130 nm CMOS process • 3 modes of operation • Counting mode • Time of Arrival: ToA • Time over threshold: ToT • Low occupancy is suited to ToT measurement, with no loss from 1 μsdeadtime Changes needed • Replace shutter based readout/acquisition scheme by continuous, deadtimeless (ZS) operation • Sustained readout of pixels with maximum flux 5 particles /cm2/25 ns • Reduced ToT range and resolution • Add bunchtime identification good within 25 ns • Timepix2 is an important step towards VELOPIX • Similar front end • Fast column bus • Data Driven readout • Simultaneous Time over Threshold and Time of Arrival measurements • Collaborating in the design • Aim to have first VELOPIX by 2012

14. ASIC development Timepix2/VELOPIX Analog requirements overlap ~100%: • Reduce timewalk: <25 ns @ 1ke-threshold • Faster preamplifier and discriminator of Timepix2 covers and exceeds this requirement • Ikrum range 5 …40nA •  sensitivity 750 … 6000 e-/25ns •  20 ke- signal returns to baseline in 660 … 83 ns • Reduced non-linearity near threshold • Analog power consumption <10 μW/pixel • Higher preamplifier gain (~50mV/ke-) • reduced ENC (σENC~ 75 e-), lower detectable charge (<500 e- ) • reduced linear range (30 ke- ) : better suited to Si –tracking • Threshold spread after tuning < 30e-

15. ASIC development • Digital functionality of VELOPIX: • Simultaneous 4 bit Time-over-threshold and time identification (12 bit) • Data loss must be kept < 0.5% in worst conditions (6kHz pixel hit-rate) • Limit ToT < 400ns • Adequate buffering & bus speeds • Sparse and data driven readout • SEU protection of logic & registers • multi-Gbit/s output links : 4 x 3.2Gb/s# • Design of superpixel (4x4), column bus and EOC logic very advanced • Total power budget <3W full chip • Radiation hardness TID 400Mrad

16. Data rates Average #particles/event 220 um ~140 um A A A A A A A A Super pixel 220 um Digital A A A A A A A A 1.0 1.0 0.6 0.6 1.3 1.3 2.6 2.6 1.0 1.0 5.3 5.3 • Numbers at highest occupancies: • average particle rate per ‘hottest’ asic ~ 5 particles/25ns = 200MHz • average pixel cluster size ~2: (pessimistic assumption, 200μm Si) • Information bits per hit pixel : 32 • 4 bit : Time over Threshold value • 12 bit : bunch identification • 16 bit : pixel address • => Single asic data rate can reach 13 Gbit/s ! • 30% data reduction can be achieved by ‘clustering’ data: • share the bunch id (12bit) and address bits between neighbor pixels. • must be done before column readout, i.e. inside pixel array ! • most efficiently done in units of 4x4 pixels = “Super pixel” • Still requires several multi-gigabit readout links • Challenge to divide work between FPGA readout and ASIC logic • Current questions: • Can we specify stream sizes to reduce workload on DAQ system • How much information should we decode for trigger pattern recognition stage?

17. RF separation foil I • Long list of severe requirements: • Vacuum tight (< 10-9mbar l/s) • Radiation hard • Low mass ( dominates the X0 contribution before the second measured point). Rigid to prevent deflection onto the sensors or pinhole leaks • Good electrical conductivity: • Mirror beam currents and shield against RF noise pick-up in front-end electronics • Thermally stable and conductive (heat load from the beam) • Material and fabrication options: • Aluminium (AlMgMn): 200-350 μm thickness: • By 5-axis milling of a single homogeneous block • Carbon Fiber Reinforced Polymer (CFRP) coated with Aluminium • Carbon Fiber (impractical, porosity and thickness vary too much) corrugation

18. RF separation foil II • Cake-shaped foil on a 3-axis milling machine • Inductive measurements + 3D measurements • Leak rate: <10−9 mbar l/s • Now more complicated shaped with 5-axis milling machine Pitch = 30 mm Depth = 6 mm Step = 16 mm Radius > 6mm

19. RF separation foil III A proof-of-technique prototype has been made Very encoring results, still some issues need to be improved 5 plies carbon fiber + epoxy + nano-particles + Al (vapor deposition)

20. Cooling studies • At the tip of the sensor Ileak≅O(100) mA/cm2 : • Thermal runaway avoided if temperature -10°C to -15°C • First ANSYS simulations done: • Model includes radial (r-1.9) and temperature dependent leakage power generated in Si. • 400 mm-thick CVD diamond substrate to the tip of the sensor • Cooling channel at 1cm from the outermost edge of silicon • Two-phase CO2 cooling capable to -35° for the cooling channel • Nominal thickness and thermal conductivities, and ROC heat loads were used • Various parameters were modified and the conclusions: • The cooling channel should be as close as possible to the silicon • The ROC power should be minimized • Thermal impedances between cooling line and silicon should be minimized • For a ROC power < 3.0 W/chip CO2 cooling is enough to avoid thermal runaway up to a dose ~1016neq/cm2. Factor 2 • Verifications with thermal mockups are planned CO2 cooling Temp -35°C Tip Temp ~ -17°C

21. Timepix telescope evolution USB1 readout USB2 readout – 700 tracks per second 6 pixel telescope planes angled in 2 dimensions to optimize resolution Device Under Test moved and rotated via remote controlled stepper motor Fine pitch strip detector with fast electronics LHC readout

22. Timepix Telescope Performance Telescope in Time Tagging configuration Timepix ToA Track Time Tagging Plane ~100ns RELAXD interface RELAXD interface/ LHC readout (Beetle, …) RELAXD interface Timepix ToT Tracking Timepix ToT Tracking DUT Cooled Scintillator Coincidence and TDC ~1ns Synchronized Trigger Logic + TDC • RELAXD readout from NIKHEF (FPGA-based) • >5kHz track rate, resolution @ DUT 1.5mm • Implemented a TDC with whichTimepixToA mode gives us ~1ns per track time stamping • Able to provide and record synchronized triggers to 40MHz readout 50,000,000 tracks recorded in 2 weeks (120 GeVπ± @ SPS) Eight different DUTs analysed* • *arXiv:1103.2739v2 [physics.ins-det]

23. Planar Silicon: Thin vs Thick s(mm) Sensor Angle (deg) Thin sensors: Direct comparison of 300 and 150 μm thick sensors in identical conditions

24. Planar sensor Resolution as a function of angle Resolution as a function of # bits 10V data (close to depletion) 100V data (overdepleted) There is an enormous gain at lower voltage Possible advantage for VELO under investigation Resolution as a function of number of bits (shown for three different angles) Input to Timepix2/Velopix design 4 bits and above are safe 3 bits is close to resolution degradation

25. 3D sensors test beam results Detailed characterization of 3d device and direct comparison to planar sensor*. Irradiated sensor also evaluated Binary resolution = 55µm / √12 = 15.9µm Resolution before and after irradiation close to binary resolution 3D binary resolution = 74.5µm / √12 = 23.1µm • *2011 JINST6 P05002 doi: 10.1088/1748-0221/6/05/P05002

26. Results from Diamond p-CVD sensorsStrasbourg telescope Preliminary Goal: produce 400 mm sensors and compare their performance with 150 mm Si at different level of irradiation First step: laboratory and test bench studies of 750 mm sensors in a test beam (CERN RD42 test beam with Strasbourg telescope) Preliminary

27. Summary • We expect the LHCb Upgrade to happen in the 2nd LHC shutdown circa 2017 • The experiment has a firm plan and timeline to achieve the upgrade • The VELO pixel module concepts and detector layout will be realizable • We are still pursuing different sensor options • The ASIC design is progressing well • R&D is progressing well in the key aspects of the detector • Prototypes are being built and will be tested to assess their performances and suitability in a harsh environment like the current VELO detector