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CSE 140 Discussion Section Midterm #2 Review

CSE 140 Discussion Section Midterm #2 Review. Mingjing Chen. JK flip-flop. Combinational logic. S. Q. J. K. R. Q’. Flip-Flops Conversion. Implement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. Solve the combinational logic design problem S = f 1 (J, K, Q)

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CSE 140 Discussion Section Midterm #2 Review

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  1. CSE 140 Discussion SectionMidterm #2 Review Mingjing Chen

  2. JK flip-flop Combinational logic S Q J K R Q’ Flip-Flops Conversion • Implement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. Solve the combinational logic design problem S = f1(J, K, Q) R = f2(J, K, Q)

  3. Flip-Flops Conversion • How to attain the specification of the combinational circuit? S = f1(J, K, Q) R = f2(J, K, Q) Truth table for combinational logic x 0 0 x x 0 1 0 0 1 0 x 0 1 1 0

  4. S Q K J R Q’ Flip-Flops Conversion Kmap for S Truth table for combinational logic JK 00 01 11 10 Qprev x 0 0 0 x 1 x 0 S = J Q’prev 1 0 0 Kmap for R 1 JK 0 x 00 01 11 10 0 1 Qprev 1 0 0 1 R = K Qprev

  5. Sequential Circuit Design • A state machine is described by the following state equations. (1). Write the state table. 2-bit states: Q1, Q0 1 input: x 1 output: y

  6. Sequential Circuit Design • Design the system with two JK flip-flops and a minimal AND-OR-NOT network.

  7. Sequential Circuit Design Kmap for J0 Q1Q0 00 01 11 10 X 0 x x 1 0 1 0 x x 0 J0 = X’Q1 Kmap for K0 Q1Q0 00 01 11 10 X x 1 0 x 0 1 x 0 0 x Kmap for J1 Kmap for K1 K0 = X’ Q1’ Q1Q0 Q1Q0 Kmap for y 00 01 11 10 00 01 11 10 X X Q1Q0 0 1 x x x x 0 1 0 0 00 01 11 10 X 1 1 1 0 x x x x 1 0 1 1 1 0 0 J1 = X’Q0+XQ0’ K1 = X’ Q0’+X Q0 1 1 1 1 0 y = Q1’+Q0

  8. Timing • Circuit implemented using two T flip-flops and a D flip-flop. • Timing characteristics: • T flip-flop: • clock-to-Q maximum delay tpcq = 2ns • clock-to-Q minimum delay tccq = 1.8ns • setup time tsetup = 1ns • hold time thold = 1.5ns • D flip-flop: • clock-to-Q maximum delay tpcq = 2.5ns • clock-to-Q minimum delay tccq = 2.3ns • setup time tsetup = 2.5ns • hold time thold = 2ns • NAND gate: • propagation delay tpd = 1ns • contamination delay tcd = 0.8ns • Inverter: • propagation delay tpd = 0.5ns • contamination delay tcd = 0.3ns

  9. Timing • How many paths? D Q T Q T Q

  10. Timing • 3 paths P1 P2 D Q T Q P3 T Q

  11. Timing • What is the maximum clock frequency of this circuit? P1: tpcq(D) +tpd(NAND) + tsetup(T) <= clock cycle 2.5 +1 + 1 <= clock cycle P2: tpcq(T) +tpd(NOT) + tsetup(D) <= clock cycle 2 +0.5 + 2.5 <= clock cycle P3: tpcq(T) +tpd(NAND) + tsetup(T) <= clock cycle 2 +1 + 1 <= clock cycle Min cycle = 5 ns  max f = 1 / min cycle = 200 MHz

  12. Timing • what is the maximum clock skew that the circuit can tolerate before it might experience a hold timeviolation? P1: tccq(D) +tcd(NAND) >= thold(T) + skew 2.3 + 0.8 >= 1.5 + skew P2: tccq(T) +tcd(NOT) >= thold(D) + skew 1.8 +0.3 >= 2 + skew P3: tccq(T) +tcd(NAND) >= thold(T) + skew 1.8 + 0.8 >= 1.5 + skew Max skew = 0.1ns

  13. Decoder & MUX • three-input Boolean function f(a, b, c) = ∑Pm(1, 2, 4, 7) + ∑ Pd(3) ab 00 01 11 10 c 0 1 0 1 0 f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) 1 1 x 1 0

  14. If inverter is not allowed f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’(b+c)+a(b+c)’+bc 0 0 1 1 1 1 In In 2 2 3 3 s1 s0 s1 s0 a c b b c Decoder & MUX • Implement the function using a minimal network of 2:4 decoders and OR gates f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ 0 1 In c 2 3 s1 s0 a b 0 1 In 2 3 s1 s0 a b

  15. Decoder & MUX • Implement the function using a minimal network of 4:1 multiplexers. f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ c 0 c’ 1 Out c’ 2 c 3 s1 s0 a b

  16. Decoder & MUX • Implement the function using a minimal network of 2:1 multiplexers f = a’c+a’b+bc+ab’c’ = af(1, b, c) + a’f(0, b, c) = a(bc+b’c’) + a’ (b+c) c 0 1 1 s b 0 c’ 0 1 s c 1 s a b

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